Datasheet LTC1289 (Analog Devices) - 4

LTC1289
U DIGITAL A D DC ELECTRICAL CH C ARA TER S I TICS The
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denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. (Note 3) LTC1289B LTC1289C SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage VCC = 3.6V ● 2.1 V VIL Low Level Input Voltage VCC = 3.0V ● 0.45 V IIH High Level Input Current VIN = VCC ● 2.5 µA IIL Low Level Input Current VIN = 0V ● – 2.5 µA VOH High Level Output Voltage VCC = 3.0V V IO = 20µA ● 2.90 IO = 400µA 2.7 2.85 VOL Low Level Output Voltage VCC = 3.0V V IO = 20µA ● 0.05 IO = 400µA 0.10 0.3 IOZ High Z Output Leakage VOUT = VCC, CS High ● 3 µA VOUT = 0V, CS High ● – 3 µA ISOURCE Output Source Current VOUT = 0V –10 mA ISINK Output Sink Current VOUT = VCC 9 mA ICC Positive Supply Current CS High ● 1.5 5 mA CS High, Power Shutdown, ACLK Off ● 1.0 10 µA IREF Reference Current VREF = 2.5V ● 10 50 µA I– Negative Supply Current CS High ● 1 50 µA
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
Two on-chip diodes are tied to each analog input which will may cause permanent damage to the device. Exposure to any Absolute conduct for analog voltages one diode drop below GND or one diode drop Maximum Rating condition for extended periods may affect device above VCC. Be careful during testing at low VCC levels, as high level analog reliability and lifetime. inputs can cause this input diode to conduct, especially at elevated
Note 2:
All voltage values are with respect to ground with DGND, AGND temperature, and cause errors for inputs near full scale. This spec allows and REF –wired together (unless otherwise noted). 50mV forward bias of either diode. This means that as long as the analog input does not exceed the supply voltage by more than 50mV, the output
Note 3:
VCC = 3V, VREF+ = 2.5V, VREF– = 0V, V – = 0V for unipolar mode code will be correct. and – 3V for bipolar mode, ACLK = 2.0MHz unless otherwise specified.
Note 8:
Channel leakage current is measured after the channel selection.
Note 4:
These specs apply for both unipolar and bipolar modes. In bipolar mode, one LSB is equal to the bipolar input span (2V
Note 9:
To minimize errors caused by noise at the chip select input, the REF) divided by 4096. For example, when V internal circuitry waits for two ACLK falling edges after a chip select falling REF = 2.5V, 1LSB(bipolar) = 2(2.5)/4096 = 1.22mV. V – = – 2.7V for bipolar mode. edge is detected before responding to control input signals. Therefore, no attempt should be made to clock an address in or data out until the
Note 5:
Integral nonlinearity is defined as the deviation of a code from a minimum chip select set-up time has elasped. See Typical Peformance straight line passing through the actual endpoints of the transfer curve. Characteristics curves for additional information (tsuCS vs VCC). The deviation is measured from the center of the quantization band.
Note 10:
Increased leakage currents at elevated temperatures cause the
Note 6:
Recommended operating conditions. S/H to droop, therefore it's recommended that fACLK ≥ 125kHz at 85°C and fACLK ≥ 15kHz at 25°C. 1289fb 4