Datasheet LTC1285, LTC1288 (Analog Devices) - 10

FabricanteAnalog Devices
Descripción3V Micropower Sampling 12-Bit A/D Converters in SO-8 Packages
Páginas / Página24 / 10 — APPLICATION INFORMATION. OVERVIEW. SERIAL INTERFACE. Figure 1. LTC1285 …
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APPLICATION INFORMATION. OVERVIEW. SERIAL INTERFACE. Figure 1. LTC1285 Operating Sequence

APPLICATION INFORMATION OVERVIEW SERIAL INTERFACE Figure 1 LTC1285 Operating Sequence

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LTC1285/LTC1288
U U W U APPLICATION INFORMATION OVERVIEW
basic design, the LTC1285 and LTC1288 differ in some respects. The LTC1285 has a differential input and has an The LTC1285 and LTC1288 are 3V micropower, 12-bit, external reference input pin. It can measure signals float- successive approximation sampling A/D converters. The ing on a DC common-mode voltage and can operate with LTC1285 typically draws 160µA of supply current when reduced spans to 1.5V. Reducing the spans allows it to sampling at 7.5kHz while the LTC1288 nominally con- achieve 366µV resolution. The LTC1288 has a two-chan- sumes 210µA of supply current when sampling at 6.6 kHz. nel input multiplexer and can convert either channel with The extra 50µA of supply current on the LTC1288 comes respect to ground or the difference between the two. The from the reference input which is intentionally tied to the reference input is tied to the supply pin. supply. Supply current drops linearly as the sample rate is reduced (see Supply Current vs Sample Rate). The ADCs
SERIAL INTERFACE
automatically power down when not performing conver- sions, drawing only leakage current. They are packaged in The 2-channel LTC1288 communicates with micropro- 8-pin SO and DIP packages. The LTC1285 and LTC1288 cessors and other external circuitry via a synchronous, operate on a single supply from 2.7V to 6V. half duplex, 4-wire serial interface. The single channel LTC1285 uses a 3-wire interface (see Operating Sequence Both the LTC1285 and the LTC1288 contain a 12-bit, in Figures 1 and 2). switched-capacitor ADC, a sample-and-hold, and a serial port (see Block Diagram). Although they share the same tCYC CS t POWER suCS DOWN CLK HI-Z NULL NULL HI-Z DOUT BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* BIT B11 B10 B9 B8 t (MSB) SMPL tCONV tDATA *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT LSB-FIRST DATA THEN FOLLOWED WITH ZEROS INDEFINITELY. tCYC CS t POWER DOWN suCS CLK NULL HI-Z BIT HI-Z DOUT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11* (MSB) tSMPL tCONV tDATA *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY. t DATA: DURING THIS TIME, THE BIAS CIRCUIT AND THE COMPARATOR POWER DOWN AND THE REFERENCE INPUT LTC1285/88 • F01 BECOMES A HIGH IMPEDANCE NODE, LEAVING THE CLK RUNNING TO CLOCK OUT LSB-FIRST DATA OR ZEROES.
Figure 1. LTC1285 Operating Sequence
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