Datasheet LTC1283 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | 3V Single Chip 10-Bit Data Acquisition System |
| Páginas / Página | 24 / 8 — APPLICATI. S I FOR ATIO. DIGITAL CONSIDERATIONS. 1. Serial Interface. 2. … |
| Formato / tamaño de archivo | PDF / 352 Kb |
| Idioma del documento | Inglés |
APPLICATI. S I FOR ATIO. DIGITAL CONSIDERATIONS. 1. Serial Interface. 2. Input Data Word. Operating Sequence
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LTC1283
O U U W U APPLICATI S I FOR ATIO
The LTC1283 is a 3V data acquisition component which previous conversion is output on the DOUT line. At the end contains the following functional blocks: of the data exchange the requested conversion begins 1. 10-bit successive approximation capacitive and CS should be brought high. After tCONV, the conver- A/D converter sion is complete and the results will be available on the next data transfer cycle. As shown below, the result of 2. Analog multiplexer (MUX) a conversion is delayed by one CS cycle from the input 3. Sample-and-hold (S&H) word requesting it. 4. Synchronous, full duplex serial interface DIN DIN WORD 1 D D IN WORD 2 IN WORD 3 5. Control and timing logic DOUT DOUT WORD 0 D D OUT WORD 1 OUT WORD 2
DIGITAL CONSIDERATIONS
t t DATA CONV DATA CONV A/D A/D TRANSFER TRANSFER CONVERSION CONVERSION LTC1283 • AI02
1. Serial Interface
The LTC1283 communicates with microprocessors and
2. Input Data Word
other external circuitry via a synchronous, full duplex, 4- The LTC1283 8-bit input data word is clocked into the DIN wire serial interface (see Operating Sequence). The shift input on the first eight rising SCLK edges after chip select clock (SCLK) synchronizes the data transfer with each bit is recognized. Further inputs on the DIN pin are then being transmitted on the falling SCLK edge and captured ignored until the next CS cycle. The eight bits of the input on the rising SCLK edge in both transmitting and receiving word are defined as follows: systems. The data is transmitted and received simulta- neously (full duplex). UNIPOLAR/ WORD BIPOLAR LENGTH DATA INPUT (DIN) WORD: Data transfer is initiated by a falling chip select (CS) signal. SGL/ ODD/ SELECT SELECT After the falling CS is recognized, an 8-bit input word is UNI MSBF WL1 WL0 DIFF SIGN 1 0 shifted into the DIN input which configures the LTC1283 for the next conversion. Simultaneously, the result of the MUX ADDRESS MSB-FIRST/ LSB-FIRST LTC1283 • AI03
Operating Sequence (Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 10-Bit Word Length)
tCYC 1 2 3 4 5 6 7 8 9 10 SCLK DON’T CARE t t SMPL CONV CS ODD/ SEL SGL/ SIGN SEL 0 MSBF WL0 DIN DIFF 1 UNI WL1 DON’T CARE D B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 OUT (SB) SHIFT CONFIGURATION SHIFT A/D RESULT OUT AND WORD IN NEW CONFIGURATION WORD IN LTC1283 • AI01 1283fb 8
O U U W U APPLICATI S I FOR ATIO
The LTC1283 is a 3V data acquisition component which previous conversion is output on the DOUT line. At the end contains the following functional blocks: of the data exchange the requested conversion begins 1. 10-bit successive approximation capacitive and CS should be brought high. After tCONV, the conver- A/D converter sion is complete and the results will be available on the next data transfer cycle. As shown below, the result of 2. Analog multiplexer (MUX) a conversion is delayed by one CS cycle from the input 3. Sample-and-hold (S&H) word requesting it. 4. Synchronous, full duplex serial interface DIN DIN WORD 1 D D IN WORD 2 IN WORD 3 5. Control and timing logic DOUT DOUT WORD 0 D D OUT WORD 1 OUT WORD 2
DIGITAL CONSIDERATIONS
t t DATA CONV DATA CONV A/D A/D TRANSFER TRANSFER CONVERSION CONVERSION LTC1283 • AI02
1. Serial Interface
The LTC1283 communicates with microprocessors and
2. Input Data Word
other external circuitry via a synchronous, full duplex, 4- The LTC1283 8-bit input data word is clocked into the DIN wire serial interface (see Operating Sequence). The shift input on the first eight rising SCLK edges after chip select clock (SCLK) synchronizes the data transfer with each bit is recognized. Further inputs on the DIN pin are then being transmitted on the falling SCLK edge and captured ignored until the next CS cycle. The eight bits of the input on the rising SCLK edge in both transmitting and receiving word are defined as follows: systems. The data is transmitted and received simulta- neously (full duplex). UNIPOLAR/ WORD BIPOLAR LENGTH DATA INPUT (DIN) WORD: Data transfer is initiated by a falling chip select (CS) signal. SGL/ ODD/ SELECT SELECT After the falling CS is recognized, an 8-bit input word is UNI MSBF WL1 WL0 DIFF SIGN 1 0 shifted into the DIN input which configures the LTC1283 for the next conversion. Simultaneously, the result of the MUX ADDRESS MSB-FIRST/ LSB-FIRST LTC1283 • AI03
Operating Sequence (Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 10-Bit Word Length)
tCYC 1 2 3 4 5 6 7 8 9 10 SCLK DON’T CARE t t SMPL CONV CS ODD/ SEL SGL/ SIGN SEL 0 MSBF WL0 DIN DIFF 1 UNI WL1 DON’T CARE D B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 OUT (SB) SHIFT CONFIGURATION SHIFT A/D RESULT OUT AND WORD IN NEW CONFIGURATION WORD IN LTC1283 • AI01 1283fb 8