Datasheet LTC1278 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | 12-Bit, 500ksps Sampling A/D Converter with Shutdown |
| Páginas / Página | 16 / 7 — PI FU CTIO S. RD (Pin 20):. IN (Pin 1):. CS (Pin 21):. REF (Pin 2):. AGND … |
| Formato / tamaño de archivo | PDF / 290 Kb |
| Idioma del documento | Inglés |
PI FU CTIO S. RD (Pin 20):. IN (Pin 1):. CS (Pin 21):. REF (Pin 2):. AGND (Pin 3):. BUSY (Pin 22):. D11 to D4 (Pins 11 to 4):
Línea de modelo para esta hoja de datos
- LTC1278-4CN#PBF LTC1278-4CSW#PBF LTC1278-4CSW#TRPBF LTC1278-4IN#PBF LTC1278-4ISW#PBF LTC1278-4ISW#TRPBF LTC1278-5CSW#PBF LTC1278-5CSW#TRPBF LTC1278-5ISW#PBF LTC1278-5ISW#TRPBF
Versión de texto del documento
LTC1278
U U U PI FU CTIO S A RD (Pin 20):
READ Input. This enables the output
IN (Pin 1):
Analog Input. 0V to 5V (Unipolar), ±2.5V (Bipolar). drivers when CS is low.
V CS (Pin 21):
The CHIP SELECT input must be low for the
REF (Pin 2):
2.42V Reference Output. Bypass to AGND (10µF tantalum in parallel with 0.1µF ceramic). ADC to recognize CONVST and RD inputs.
AGND (Pin 3):
Analog Ground.
BUSY (Pin 22):
The BUSY output shows the converter status. It is low when a conversion is in progress.
D11 to D4 (Pins 11 to 4):
Three-State Data Outputs. D11 is the Most Significant Bit.
VSS (Pin 23):
Negative Supply. – 5V for bipolar opera- tion. Bypass to AGND with 0.1µF ceramic. Analog
DGND (Pin 12):
Digital Ground. ground for unipolar operation.
D3 to D0 (Pins 13 to 16):
Three-State Data Outputs.
AVDD (Pin 24):
Positive Supply, 5V. Bypass to AGND
DVDD (Pin 17 ):
Digital Power Supply, 5V. Tie to AVDD pin. (10µF tantalum in parallel with 0.1µF ceramic).
SHDN (Pin 18):
Power Shutdown.
CONVST (Pin 19):
Conversion Start Signal. This active low signal starts a conversion on its falling edge (to recognize CONVST, CS has to be low).
U U W FU CTIO AL BLOCK DIAGRA
CSAMPLE A AV IN DD ZEROING SWITCH DVDD 2.42V REF VSS (0V FOR UNIPOLAR MODE V OR –5V FOR BIPOLAR MODE) REF 12-BIT CAPACITIVE DAC COMPARATOR 12 AGND 12 D11 SUCCESSIVE APPROXIMATION • OUTPUT LATCHES • REGISTER • DGND D0 LTC1278 • BD INTERNAL CONTROL LOGIC CLOCK SHDN CONVST RD CS BUSY 7
U U U PI FU CTIO S A RD (Pin 20):
READ Input. This enables the output
IN (Pin 1):
Analog Input. 0V to 5V (Unipolar), ±2.5V (Bipolar). drivers when CS is low.
V CS (Pin 21):
The CHIP SELECT input must be low for the
REF (Pin 2):
2.42V Reference Output. Bypass to AGND (10µF tantalum in parallel with 0.1µF ceramic). ADC to recognize CONVST and RD inputs.
AGND (Pin 3):
Analog Ground.
BUSY (Pin 22):
The BUSY output shows the converter status. It is low when a conversion is in progress.
D11 to D4 (Pins 11 to 4):
Three-State Data Outputs. D11 is the Most Significant Bit.
VSS (Pin 23):
Negative Supply. – 5V for bipolar opera- tion. Bypass to AGND with 0.1µF ceramic. Analog
DGND (Pin 12):
Digital Ground. ground for unipolar operation.
D3 to D0 (Pins 13 to 16):
Three-State Data Outputs.
AVDD (Pin 24):
Positive Supply, 5V. Bypass to AGND
DVDD (Pin 17 ):
Digital Power Supply, 5V. Tie to AVDD pin. (10µF tantalum in parallel with 0.1µF ceramic).
SHDN (Pin 18):
Power Shutdown.
CONVST (Pin 19):
Conversion Start Signal. This active low signal starts a conversion on its falling edge (to recognize CONVST, CS has to be low).
U U W FU CTIO AL BLOCK DIAGRA
CSAMPLE A AV IN DD ZEROING SWITCH DVDD 2.42V REF VSS (0V FOR UNIPOLAR MODE V OR –5V FOR BIPOLAR MODE) REF 12-BIT CAPACITIVE DAC COMPARATOR 12 AGND 12 D11 SUCCESSIVE APPROXIMATION • OUTPUT LATCHES • REGISTER • DGND D0 LTC1278 • BD INTERNAL CONTROL LOGIC CLOCK SHDN CONVST RD CS BUSY 7