Datasheet LTC1273, LTC1275, LTC1276 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | 12-Bit, 300ksps Sampling A/D Converters with Reference |
| Páginas / Página | 24 / 9 — FU CTI. VSS (Pin 23):. VDD (Pin 24):. NC (Pin 23):. Table 1. Data Bus … |
| Formato / tamaño de archivo | PDF / 329 Kb |
| Idioma del documento | Inglés |
FU CTI. VSS (Pin 23):. VDD (Pin 24):. NC (Pin 23):. Table 1. Data Bus Output, CS and RD = LOW. Pin 4. Pin 5. Pin 6. Pin 7. Pin 8. Pin 9
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Versión de texto del documento
LTC1273 LTC1275/LTC1276
U U O U PI FU CTI S VSS (Pin 23):
Negative Supply. – 5V for LTC1275/
VDD (Pin 24):
Positive Supply, 5V. Bypass to AGND LTC1276. Bypass to AGND with 0.1µF ceramic. (10µF tantalum in parallel with 0.1µF ceramic).
NC (Pin 23):
No Connection for LTC1273.
Table 1. Data Bus Output, CS and RD = LOW Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16
MNEMONIC* D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8 HBEN = LOW DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 HBEN = HIGH DB11 DB10 DB9 DB8 LOW LOW LOW LOW DB11 DB10 DB9 DB8 *D11...D0/8 are the ADC data output pins. DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
U U W FU TIO AL BLOCK DIAGRA
SAMPLE V V DD SS (NC ON LTC1273) CSAMPLE COMPARATOR SAMPLE A – IN HOLD + D11 12 12 SUCCESSIVE OUTPUT • 12-BIT APPROXIMATION • LATCHES CAPACITIVE REGISTER • VREF(OUT) DAC D0/8 BUSY 2.42V REFERENCE CS INTERNAL CONTROL RD CLOCK LOGIC AGND DGND HBEN LTC1273/75/76 • FBD
TEST CIRCUITS Load Circuits for Access Time Load Circuits for Output Float Delay
5V 5V 3k 3k DBN DBN DBN DBN 3k CL CL 3k 10pF 10pF DGND DGND DGND DGND A) HIGH-Z TO VOH (t3) B) HIGH-Z TO VOL (t3) A) VOH TO HIGH-Z B) VOL TO HIGH-Z AND VOL TO VOH (t6) AND VOH TO VOL (t6) 1273/75/76 • TA08 1273/75/76 • TA07 127356fa 9
U U O U PI FU CTI S VSS (Pin 23):
Negative Supply. – 5V for LTC1275/
VDD (Pin 24):
Positive Supply, 5V. Bypass to AGND LTC1276. Bypass to AGND with 0.1µF ceramic. (10µF tantalum in parallel with 0.1µF ceramic).
NC (Pin 23):
No Connection for LTC1273.
Table 1. Data Bus Output, CS and RD = LOW Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16
MNEMONIC* D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8 HBEN = LOW DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 HBEN = HIGH DB11 DB10 DB9 DB8 LOW LOW LOW LOW DB11 DB10 DB9 DB8 *D11...D0/8 are the ADC data output pins. DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
U U W FU TIO AL BLOCK DIAGRA
SAMPLE V V DD SS (NC ON LTC1273) CSAMPLE COMPARATOR SAMPLE A – IN HOLD + D11 12 12 SUCCESSIVE OUTPUT • 12-BIT APPROXIMATION • LATCHES CAPACITIVE REGISTER • VREF(OUT) DAC D0/8 BUSY 2.42V REFERENCE CS INTERNAL CONTROL RD CLOCK LOGIC AGND DGND HBEN LTC1273/75/76 • FBD
TEST CIRCUITS Load Circuits for Access Time Load Circuits for Output Float Delay
5V 5V 3k 3k DBN DBN DBN DBN 3k CL CL 3k 10pF 10pF DGND DGND DGND DGND A) HIGH-Z TO VOH (t3) B) HIGH-Z TO VOL (t3) A) VOH TO HIGH-Z B) VOL TO HIGH-Z AND VOL TO VOH (t6) AND VOH TO VOL (t6) 1273/75/76 • TA08 1273/75/76 • TA07 127356fa 9