Datasheet LTC1272 (Analog Devices) - 10

LTC1272
APPLICATIONS INFORMATION
CS & RD t2 tCONV BUSY ≥ 40ns* t13 CLK IN t14 DB11 DB10 DB1 DB0 (MSB) (LSB) UNCERTAIN CONVERSION TIME FOR 30ns < t14 < 180ns LTC1272 • F05 * THE LTC1272 IS ALSO COMPATIBLE WITH THE AD7572 SYNCHRONIZATION MODES.
Figure 5. RD and CLK IN for Synchronous Operation
as in Figure 5. Nevertheless, even without observing this guideline, the LTC1272 is still compatible with AD7572 CLK OUT C1 LTC1272 18 synchronization modes, with no increase in linearity error. This means that either the falling or rising edge of CLK IN C2 17 CLOCK may be near RD’s falling edge. CLK IN 1M
Driving the Analog Input
NOTES: LTC1272-3 – 4MHz CRYSTAL/CERAMIC RESONATOR The analog input of the LTC1272 is much easier to drive LTC1272-8 – 1.6MHz CRYSTAL/CERAMIC RESONATOR LTC1272 • F06 than that of the AD7572. The input current is not modulated by the DAC as in the AD7572. It has only one small current
Figure 6. LTC1272 Internal Clock Circuit
spike from charging the sample-and-hold capacitor at the end of the conversion. During the conversion the analog to CLK IN. For an external clock the duty cycle is not input draws only DC current. The only requirement is that critical. An inverted CLK IN signal will appear at the CLK the amplifier driving the analog input must settle after the OUT pin as shown in the operating waveforms of Figure 7. small current spike before the next conversion is started. Capacitance on the CLK OUT pin should be minimized for Any op amp that settles in 1µs to small current transients best analog performance. will allow maximum speed operation. If slower op amps
Internal Reference
are used, more settling time can be provided by increasing the time between conversions. Suitable devices capable The LTC1272 has an on-chip, temperature compensated, of driving the LTC1272 AIN input include the LT1006 and curvature corrected, bandgap reference, which is factory LT1007 op amps. trimmed to 2.42V ±1%. It is internally connected to the DAC and is also available at pin 2 to provide up to 1mA
Internal Clock Oscillator
current to an external load. Figure 6 shows the LTC1272 internal clock circuit. A crystal For minimum code transition noise the reference output or ceramic resonator may be connected between CLK IN should be decoupled with a capacitor to filter wideband (Pin 17) and CLK OUT (Pin 18) to provide a clock oscillator noise from the reference (10µF tantalum in parallel with for ADC timing. Alternatively the crystal/resonator may be a 0.1µF ceramic). A simplified schematic of the reference omitted and an external clock source may be connected with its recommended decoupling is shown in Figure 8. 1272fc 10 For more information www.linear.com/1272 Document Outline FEATURES APPLICATIONS DESCRIPTION TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION CONVERTER CHARACTERISTICS INTERNAL REFERENCE CHARACTERISTICS DIGITAL AND DC ELECTRICAL CHARACTERISTICS DYNAMIC ACCURACY ANALOG INPUT TIMING CHARACTERISTICS PIN FUNCTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION REVISION HISTORY PACKAGE DESCRIPTION