LTC1197/LTC1197L LTC1199/LTC1199L UUUPI FU CTIO SCS (Pin 1): Chip Select Input. A logic low on this input DIN (Pin 5): LTC1199/LTC1199L Digital Data Input. The enables the LTC1197/LTC1197L/LTC1199/LTC1199L. A/D configuration word is shifted into this input. Power shutdown is activated when CS is brought high. DOUT (Pin 6): Digital Data Output. The A/D conversion + IN, CH0 (Pin 2): Analog Input. This input must be free of result is shifted out of this output. noise with respect to GND. CLK (Pin 7): Shift Clock. This clock synchronizes the serial – IN, CH1 (Pin 3): Analog Input. This input must be free of data transfer. noise with respect to GND. VCC (Pin 8): Positive Supply. This supply must be kept GND (Pin 4): Analog Ground. GND should be tied directly free of noise and ripple by bypassing directly to the to an analog ground plane. analog ground plane. For LTC1199/LTC1199L, VREF is tied internally to this pin. VREF (Pin 5): LTC1197/LTC1197L Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. WBLOCK DIAGRA VCC CS (D CLK IN) BIAS AND SERIAL PORT D SHUTDOWN CIRCUIT OUT + IN (CH0) CSMPL – SAR – IN (CH1) + MICROPOWER COMPARATOR CAPACITIVE DAC GND VREF PIN NAMES IN PARENTHESES REFER TO THE LTC1199/LTC1199L 10