Datasheet LTC1099 (Analog Devices) - 7

LTC1099
U U U FUNCTIONAL DESCRIPTIO
Figure 5 shows the functional block diagram for the VREF LTC1099 2-step flash ADC. It consists of two 4-bit flash B7 converters, a 4-bit DAC and a differencing circuit. The MS B6 conversion process proceeds as follows: VIN 4-BIT FLASH B5 1. At the start of the conversion, the on-board sample- B4 and-hold switches from the sample to the hold mode. This is a true sample-and-hold with an acquisition time of 240ns, an aperture time of 110ns and a tracking rate of 2.5V/µs. 4-BIT DAC 2. The held input voltage is converted by the 4-bit MS- Flash ADC. This generates the upper or most significant 4-bits of the 8-bit output. + ∑ – 3. A 4-bit approximation, from the DAC output, is sub- REMAINDER tracted from the held input voltage. VREF/16 4. The LS-Flash ADC converts the difference between the B3 held input voltage and the DAC approximation. This LS B2 4-BIT generates the lower or least significant (LS) 4-bits of FLASH B1 the 8-bit output. The LS-Flash reference is one six- B0 teenth of the MS-Flash reference. This effectively mul- tiplies the difference by 16. 1099 F05
Figure 5. 8-Bit 2-Step Semiflash A/D
5. Upon the completion of the LS 4-bit flash the eight output latches are updated simultaneously. At the same accomplish this function in a simple, although not straight time, the sample-and-hold is switched from the hold forward,␣ manner. mode to the acquire mode in preparation for the next conversion. Figure 6 shows the six input switched capacitor compara- tor. Intuitively, the comparator is easy to understand by The advantage of this approach is the reduction in the noting that the common connection between the two input amount of hardware required. A full flash converter re- capacitors, C1 and C2, acts like a virtual ground. In quires 255 comparators while this approach requires only operational amplifier circuits, current is summed at the 31. The price paid for this reduction in hardware is an virtual ground node. Input voltage is converted to current increase in conversion time. A full flash converter requires by the input resistors. In the switched capacitor compara- only one comparison cycle while this approach requires tor, input voltage is converted to charge by the input two comparison cycles, hence 2-step flash. capacitors and these charges are summed at the virtual This architecture is further simplified in the LTC1099 by ground node. reusing the MS-Flash hardware to do the LS-Flash. This A major advantage of this technique is that the switch-on reduces the number of comparators from 31 to 16. This is impedance has no affect on accuracy as long as sufficient possible because the MS and LS conversions are done at time exists to fully charge and discharge the capacitors. different times. During the first time period the T+ and T To take the simple block diagram of Figure 5 and reconfigure Z switches are closed. This forces the common node between C1 and C2 it to reuse the MS-Flash to do the LS-Flash is conceptually to an arbitrary bias voltage. Since the capacitors subtract simple, but from a hardware point of view is not practical. out this voltage, it may be considered, for the sake of this A new six input switched capacitor comparator is used to discussion, to be exactly zero (i.e., virtual ground). Note 7