Datasheet LTC1096, LTC1096L, LTC1098, LTC1098L (Analog Devices) - 4
| Fabricante | Analog Devices |
| Descripción | Micropower Sampling 8-Bit Serial I/O A/D Converters |
| Páginas / Página | 32 / 4 — RECOMMENDED OPERATING CONDITIONS. LTC1096/LTC1098. SYMBOL. PARAMETER. … |
| Formato / tamaño de archivo | PDF / 292 Kb |
| Idioma del documento | Inglés |
RECOMMENDED OPERATING CONDITIONS. LTC1096/LTC1098. SYMBOL. PARAMETER. CONDITIONS. MIN. TYP. MAX. UNITS. VCC = 3V Operation
Línea de modelo para esta hoja de datos
- LTC1096ACN8#PBF LTC1096ACS8#PBF LTC1096ACS8#TRPBF LTC1096AIN8#PBF LTC1096AIS8#PBF LTC1096AIS8#TRPBF LTC1096CN8#PBF LTC1096CN8#PBF LTC1096CS8#PBF LTC1096CS8#PBF LTC1096CS8#TRPBF LTC1096CS8#TRPBF LTC1096IN8#PBF LTC1096IN8#PBF LTC1096IS8#PBF LTC1096IS8#PBF LTC1096IS8#TRPBF LTC1096IS8#TRPBF LTC1096LCS8#PBF LTC1096LCS8#TRPBF LTC1096LIS8#PBF LTC1096LIS8#TRPBF
- LTC1098ACN8#PBF LTC1098ACS8#PBF LTC1098ACS8#TRPBF LTC1098CN8#PBF LTC1098CN8#PBF LTC1098CS8#PBF LTC1098CS8#PBF LTC1098CS8#TRPBF LTC1098CS8#TRPBF LTC1098IN8#PBF LTC1098IN8#PBF LTC1098IS8#PBF LTC1098IS8#PBF LTC1098IS8#TRPBF LTC1098IS8#TRPBF LTC1098LCS8#PBF LTC1098LCS8#TRPBF LTC1098LIS8#PBF LTC1098LIS8#TRPBF
Versión de texto del documento
LTC1096/LTC1096L LTC1098/LTC1098L
RECOMMENDED OPERATING CONDITIONS LTC1096/LTC1098 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tWHCS CS High Time Between Data Transfer Cycles VCC = 5V 1 μs tWLCS CS Low Time During Data Transfer LTC1096, fCLK = 500kHz 28 μs LTC1098, fCLK = 500kHz 28 μs
VCC = 3V Operation
fCLK Clock Frequency VCC = 3V 25 250 kHz tCYC Total Cycle Time LTC1096, fCLK = 250kHz 58 μs LTC1098, fCLK = 250kHz 58 μs thDI Hold Time, DIN After CLK↑ VCC = 3V 450 ns tsuCS Setup Time CS↓ Before First CLK↑ (See Operating Sequence) VCC = 3V, LTC1096 1 μs VCC = 3V, LTC1098 1 μs tWAKEUP Wake-Up Time CS↓ Before First CLK↓ After First CLK↑ VCC = 3V, LTC1096 10 μs (See Figure 1 LTC1096 Operating Sequence) Wake-Up Time CS↓ Before MSBF Bit CLK↓ VCC = 3V, LTC1098 10 μs (See Figure 2 LTC1098 Operating Sequence) tsuDI Setup Time, DIN Stable Before CLK↑ VCC = 3V 1 μs tWHCLK CLK High Time VCC = 3V 1.6 μs tWLCLK CLK Low Time VCC = 3V 1.6 μs tWHCS CS High Time Between Data Transfer Cycles VCC = 3V 2 μs tWLCS CS Low Time During Data Transfer LTC1096, fCLK = 250kHz 56 μs LTC1098, fCLK = 250kHz 56 μs
LTC1096L/LTC1098L SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage 2.65 4.0 V fCLK Clock Frequency VCC = 2.65V 25 250 kHz tCYC Total Cycle Time LTC1096L, fCLK = 250kHz 58 μs LTC1098L, fCLK = 250kHz 58 μs thDI Hold Time, DIN After CLK↑ VCC = 2.65V 450 ns tsuCS Setup Time CS↓ Before First CLK↑ (See Operating Sequence) VCC = 2.65V, LTC1096L 1 μs VCC = 2.65V, LTC1098L 1 μs tWAKEUP Wake-Up Time CS↓ Before First CLK↓ After First CLK↑ VCC = 2.65V, LTC1096L 10 μs (See Figure 1 LTC1096L Operating Sequence) Wake-Up Time CS↓ Before MSBF Bit CLK↓ VCC = 2.65V, LTC1098L 10 μs (See Figure 2 LTC1098L Operating Sequence) tsuDI Setup Time, DIN Stable Before CLK↑ VCC = 2.65V 1 μs tWHCLK CLK High Time VCC = 2.65V 1.6 μs tWLCLK CLK Low Time VCC = 2.65V 1.6 μs tWHCS CS High Time Between Data Transfer Cycles VCC = 2.65V 2 μs tWLCS CS Low Time During Data Transfer LTC1096L, fCLK = 250kHz 56 μs LTC1098L, fCLK = 250kHz 56 μs 10968fc 4
RECOMMENDED OPERATING CONDITIONS LTC1096/LTC1098 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tWHCS CS High Time Between Data Transfer Cycles VCC = 5V 1 μs tWLCS CS Low Time During Data Transfer LTC1096, fCLK = 500kHz 28 μs LTC1098, fCLK = 500kHz 28 μs
VCC = 3V Operation
fCLK Clock Frequency VCC = 3V 25 250 kHz tCYC Total Cycle Time LTC1096, fCLK = 250kHz 58 μs LTC1098, fCLK = 250kHz 58 μs thDI Hold Time, DIN After CLK↑ VCC = 3V 450 ns tsuCS Setup Time CS↓ Before First CLK↑ (See Operating Sequence) VCC = 3V, LTC1096 1 μs VCC = 3V, LTC1098 1 μs tWAKEUP Wake-Up Time CS↓ Before First CLK↓ After First CLK↑ VCC = 3V, LTC1096 10 μs (See Figure 1 LTC1096 Operating Sequence) Wake-Up Time CS↓ Before MSBF Bit CLK↓ VCC = 3V, LTC1098 10 μs (See Figure 2 LTC1098 Operating Sequence) tsuDI Setup Time, DIN Stable Before CLK↑ VCC = 3V 1 μs tWHCLK CLK High Time VCC = 3V 1.6 μs tWLCLK CLK Low Time VCC = 3V 1.6 μs tWHCS CS High Time Between Data Transfer Cycles VCC = 3V 2 μs tWLCS CS Low Time During Data Transfer LTC1096, fCLK = 250kHz 56 μs LTC1098, fCLK = 250kHz 56 μs
LTC1096L/LTC1098L SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage 2.65 4.0 V fCLK Clock Frequency VCC = 2.65V 25 250 kHz tCYC Total Cycle Time LTC1096L, fCLK = 250kHz 58 μs LTC1098L, fCLK = 250kHz 58 μs thDI Hold Time, DIN After CLK↑ VCC = 2.65V 450 ns tsuCS Setup Time CS↓ Before First CLK↑ (See Operating Sequence) VCC = 2.65V, LTC1096L 1 μs VCC = 2.65V, LTC1098L 1 μs tWAKEUP Wake-Up Time CS↓ Before First CLK↓ After First CLK↑ VCC = 2.65V, LTC1096L 10 μs (See Figure 1 LTC1096L Operating Sequence) Wake-Up Time CS↓ Before MSBF Bit CLK↓ VCC = 2.65V, LTC1098L 10 μs (See Figure 2 LTC1098L Operating Sequence) tsuDI Setup Time, DIN Stable Before CLK↑ VCC = 2.65V 1 μs tWHCLK CLK High Time VCC = 2.65V 1.6 μs tWLCLK CLK Low Time VCC = 2.65V 1.6 μs tWHCS CS High Time Between Data Transfer Cycles VCC = 2.65V 2 μs tWLCS CS Low Time During Data Transfer LTC1096L, fCLK = 250kHz 56 μs LTC1098L, fCLK = 250kHz 56 μs 10968fc 4