Datasheet AD8016 (Analog Devices) - 10
Fabricante | Analog Devices |
Descripción | Full Rate ADSL Line Driver With Powerdown |
Páginas / Página | 21 / 10 — Data Sheet. AD8016. –30. –40. (0,0). ) –50. (0,1). N –60. N ( –60. (1,0). … |
Revisión | C |
Formato / tamaño de archivo | PDF / 517 Kb |
Idioma del documento | Inglés |
Data Sheet. AD8016. –30. –40. (0,0). ) –50. (0,1). N –60. N ( –60. (1,0). –70. O –70. –80. PWDN1, PWDN0 = (1,1). –90. –100. DIFFERENTIAL OUTPUT (V p-p)
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Data Sheet AD8016 –30 –30 –40 –40 (0,0) ) –50 ) –50 Bc Bc d d ( (0,0) (0,1) N –60 N ( –60 IO IO RT (1,0) RT –70 (0,1) O O –70 T T S (1,0) S DI DI –80 –80 PWDN1, PWDN0 = (1,1) PWDN1, PWDN0 = (1,1) –90 –90 –100 –100
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0 5 10 15 20 25 30 35 40
-020
0 5 10 15 20 25 30 35 40
02 9-
DIFFERENTIAL OUTPUT (V p-p) DIFFERENTIAL OUTPUT (V p-p)
01 01019 01 Figure 18. Distortion vs. Output Voltage; Second Harmonic, VS = ±12 V, Figure 21. Distortion vs. Output Voltage; Third Harmonic, VS = ±12 V, G = +10, f = 1 MHz, RL = 50 Ω, Differential G = +10, f = 1 MHz, RL = 50 Ω, Differential
–30 –30 –40 –40 (0,0) c) –50 c) –50 B B d d ( ( N (0,1) ON IO TI –60 T –60 R OR (0,0) O (1,0) T (0,1) T IS S D –70 DI –70 (1,0) –80 –80 PWDN1, PWDN0 = (1,1) PWDN1, PWDN0 = (1,1) –90 –90
24 0
0 5 10 15 20
021 9-
0 5 10 15 20
9-
DIFFERENTIAL OUTPUT (V p-p) DIFFERENTIAL OUTPUT (V p-p)
101 0101 0 Figure 19. Distortion vs. Output Voltage; Second Harmonic, VS = ±6 V, Figure 22. Distortion vs. Output Voltage, Third Harmonic, VS = ±6 V, G = +10, G = +10, f = 1 MHz, RL = 50 Ω, Differential f = 1 MHz, RL = 50 Ω, Differential
–30 3 ) –35 B 0 –40 SE (d –3 N O (1,1) –45 –6 c) B ESP d ( –50 Y R –9 (1,0) (0,0) C N TION –55 E –12 (0,1) U (0,1) OR T –60 EQ –15 R IS (1,0) D F –65 D –18 E (0,0) IZ L –70 A –21 M R –75 O –24 VIN = 40mV p-p G = +5 PWDN1, PWDN0 = (1,1) N RL = 100Ω –80 –27
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0 100 200 300 400 500 600
022 02 9-
1 10 100 500 PEAK OUTPUT CURRENT (mA) FREQUENCY (MHz)
019- 0101 01 Figure 20. Distortion vs. Peak Output Current; Third Harmonic, VS = ±6 V, Figure 23. Frequency Response; VS = ±12 V, @ PWDN1, PWDN0 Codes G = +5, RL = 5 Ω, f = 100 kHz, Single-Ended Rev. C | Page 9 of 20 Document Outline Features Pin Configurations General Description Revision History Specifications Logic Inputs (CMOS Compatible Logic) Absolute Maximum Ratings Maximum Power Dissipation ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuts Theory of Operation Power Supply and Decoupling Feedback Resistor Selection Bias Pin and PWDN Features Thermal Shutdown Applications Information Multitone Power Ratio (MTPR) Generating DMT Power Dissipation Thermal Enhancements and PCB Layout Thermal Testing Air Flow Test Conditions DUT Power Thermal Resistance PCB Dimensions of a Differential Driver Circuit Experimental Results Outline Dimensions Ordering Guide