Datasheet AD8033, AD8034 (Analog Devices) - 6

FabricanteAnalog Devices
DescripciónLow Cost, 80 MHz FastFET Op Amps
Páginas / Página24 / 6 — AD8033/AD8034. ABSOLUTE MAXIMUM RATINGS. Table 4. Parameter Rating. 2.0. …
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AD8033/AD8034. ABSOLUTE MAXIMUM RATINGS. Table 4. Parameter Rating. 2.0. W N (. 1.5. IO AT. SOT-23-8. SOIC-8. S S. R DI 1.0. W O. SC70-5. IM 0.5

AD8033/AD8034 ABSOLUTE MAXIMUM RATINGS Table 4 Parameter Rating 2.0 W N ( 1.5 IO AT SOT-23-8 SOIC-8 S S R DI 1.0 W O SC70-5 IM 0.5

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AD8033/AD8034 ABSOLUTE MAXIMUM RATINGS
If the rms signal levels are indeterminate, consider the worst case,
Table 4.
when VOUT = VS/4 for RL to midsupply
Parameter Rating
P Supply Voltage 26.4 V D = (VS × IS) + (VS/4)2/RL Power Dissipation See Figure 5 In single-supply operation with RL referenced to VS−, worst case Common-Mode Input Voltage 26.4 V is VOUT = VS/2. Differential Input Voltage 1.4 V
2.0
Storage Temperature Range −65°C to +125°C
)
Operating Temperature Range −40°C to +85°C
W N (
Lead Temperature (Soldering 10 sec) 300°C
1.5 IO AT SOT-23-8 SOIC-8 IP
Stresses above those listed under Absolute Maximum Ratings
S S
may cause permanent damage to the device. This is a stress
R DI 1.0 E
rating only; functional operation of the device at these or any
W O
other conditions above those indicated in the operational
P SC70-5 UM
section of this specification is not implied. Exposure to absolute
IM 0.5
maximum rating conditions for extended periods may affect
AX M
device reliability.
0 MAXIMUM POWER DISSIPATION –60 –40 –20 0 20 40 60 80 100
0504-
AMBIENT TEMPERATURE (°C)
92 The maximum safe power dissipation in the AD8033/AD8034 02 packages is limited by the associated rise in junction temperature Figure 5. Maximum Power Dissipation vs. (T Ambient Temperature for a 4-Layer Board J) on the die. The plastic that encapsulates the die locally reaches the junction temperature. At approximately 150°C, Airflow increases heat dissipation, effectively reducing θJA. In which is the glass transition temperature, the plastic changes its addition, more metal directly in contact with the package leads properties. Even temporarily exceeding this temperature limit from metal traces, through holes, ground, and power planes can change the stresses that the package exerts on the die, reduces the θJA. Care must be taken to minimize parasitic permanently shifting the parametric performance of the AD8033/ capacitances at the input leads of high speed op amps as discussed AD8034. Exceeding a junction temperature of 175°C for an in the Layout, Grounding, and Bypassing Considerations section. extended period can result in changes in silicon devices, potentially Figure 5 shows the maximum power dissipation in the package causing failure. vs. the ambient temperature for the 8-lead SOIC (125°C/W), The still-air thermal properties of the package and PCB (θJA), 5-lead SC70 (210°C/W), and 8-lead SOT-23 (160°C/W) packages ambient temperature (TA), and the total power dissipated in the on a JEDEC standard 4-layer board. θJA values are approximations. package (PD) determine the junction temperature of the die.
OUTPUT SHORT CIRCUIT
The junction temperature can be calculated as Shorting the output to ground or drawing excessive current for TJ = TA + (PD × θJA) the AD8033/AD8034 will likely cause catastrophic failure. PD is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (V
ESD CAUTION
S) times the quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package PD = Quiescent Power + (Total Drive Power − Load Power) P 2 D = [VS × IS] + [(VS/2) × (VOUT/RL)] − [VOUT /RL] RMS output voltages should be considered. If RL is referenced to −VS, as in single-supply operation, the total drive power is VS × IOUT. Rev. D | Page 6 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION OUTPUT SHORT CIRCUIT ESD CAUTION TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS THEORY OF OPERATION OUTPUT STAGE DRIVE AND CAPACITIVE LOAD DRIVE INPUT OVERDRIVE INPUT IMPEDANCE THERMAL CONSIDERATIONS LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS BYPASSING GROUNDING LEAKAGE CURRENTS INPUT CAPACITANCE APPLICATIONS INFORMATION HIGH SPEED PEAK DETECTOR ACTIVE FILTERS WIDEBAND PHOTODIODE PREAMP OUTLINE DIMENSIONS ORDERING GUIDE