Datasheet AD8029, AD8030, AD8040 (Analog Devices) - 7

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Data Sheet AD8029/AD8030/AD8040 ABSOLUTE MAXIMUM RATINGS Table 4. AD8029/AD8030/AD8040 Stress Ratings
RMS output voltages should be considered. If RL is referenced to V
Parameter Rating
S–, as in single-supply operation, then the total drive power is V Supply Voltage 12.6 V S × IOUT. Power Dissipation See Figure 6 If the rms signal levels are indeterminate, consider the worst Common-Mode Input Voltage ±V case, when V S ± 0.5 V OUT = VS/4 for RL to midsupply: Differential Input Voltage ±1.8 V V 2 /4 Storage Temperature –65°C to +125°C P = (V × I ) ( ) S D S S + R Operating Temperature Range –40°C to +125°C L Lead Temperature Range 300°C In single-supply operation with RL referenced to VS–, worst case (Soldering 10 sec) is VOUT = VS/2. Junction Temperature 150°C Airflow increases heat dissipation, effectively reducing θJA. Also, Stresses above those listed under Absolute Maximum Ratings more metal directly in contact with the package leads from may cause permanent damage to the device. This is a stress metal traces, through holes, ground, and power planes reduce rating only; functional operation of the device at these or any the θJA. Care must be taken to minimize parasitic capacitances other conditions above those indicated in the operational at the input leads of high speed op amps, as discussed in the section of this specification is not implied. Exposure to absolute PCB Layout section. maximum rating conditions for extended periods may affect Figure 6 shows the maximum safe power dissipation in the device reliability. package versus the ambient temperature for the SOIC-8
MAXIMUM POWER DISSIPATION
(125°C/W), SOT23-8 (160°C/W), SOIC-14 (90°C/W), The maximum safe power dissipation in the AD8029/AD8030/ TSSOP-14 (120°C/W), and SC70-6 (208°C/W) packages on a AD8040 package is limited by the associated rise in junction JEDEC standard 4-layer board. θJA values are approximations. temperature (T
2.5
J) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 150°C, which is the glass transition temperature, the plastic
2.0
changes its properties. Even temporarily exceeding this
SOIC-14
temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric
1.5 TSSOP-14
performance of the AD8029/AD8030/AD8040. Exceeding a
SOIC-8
junction temperature of 175°C for an extended period can
1.0 SOT-23-8
result in changes in silicon devices, potentially causing failure. The still-air thermal properties of the package and PCB (θ
SC70-6
JA),
0.5
ambient temperature (T
MAXIMUM POWER DISSIPATION (W)
A), and the total power dissipated in the package (PD) determine the junction temperature of the die.
0
The junction temperature can be calculated as
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120 AMBIENT TEMPERATURE (°C)
03679-A-018 TJ = TA + (PD × θJA) Figure 6. Maximum Power Dissipation The power dissipated in the package (PD) is the sum of the
Output Short Circuit
quiescent power dissipation and the power dissipated in the Shorting the output to ground or drawing excessive current package due to the load drive for all outputs. The quiescent from the AD8029/AD8030/AD8040 could cause catastrophic power is the voltage between the supply pins (VS) times the failure. quiescent current (IS). Assuming the load (RL) is referenced to midsupply, the total drive power is V
ESD CAUTION
S/2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = Quiescent Power + (Total Drive Power – Load Power)   2 P = (V × I ) S V O V UT O V UT D S S + × –   2 R  L  RL Rev. B | Page 7 of 24 Document Outline Features Applications Connection Diagrams General Description Table of Contents Revision History Specifications Specifications with ±5 V Supply Specifications with +5 V Supply Specifications with +3 V Supply Absolute Maximum Ratings Maximum Power Dissipation Output Short Circuit ESD Caution Typical Performance Characteristics Theory of Operation Input Stage Output Stage Applications Wideband Operation Output Loading Sensitivity Disable Pin Circuit Considerations PCB Layout Grounding Power Supply Bypassing Design Tools and Technical Support Outline Dimensions Ordering Guide