Datasheet MCP6291, MCP6291R, MCP6292, MCP6293, MCP6294, MCP6295 (Microchip) - 5
| Fabricante | Microchip |
| Descripción | The Microchip Technology MCP6291/1R/2/3/4/5 family of operational amplifiers (op amps) provide wide bandwidth for the current |
| Páginas / Página | 36 / 5 — MCP6291/1R/2/3/4/5. 2.0. TYPICAL PERFORMANCE CURVES. Note:. 12%. 25%. … |
| Formato / tamaño de archivo | PDF / 678 Kb |
| Idioma del documento | Inglés |
MCP6291/1R/2/3/4/5. 2.0. TYPICAL PERFORMANCE CURVES. Note:. 12%. 25%. 11%. 840 Samples. 840 Samples V. 10%. CM = VSS. c 20% T
Línea de modelo para esta hoja de datos
Versión de texto del documento
MCP6291/1R/2/3/4/5 2.0 TYPICAL PERFORMANCE CURVES Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, and CS is tied low.
12% 25% 11% es 840 Samples c es 840 Samples V 10% V CM = VSS n CM = VSS c 20% T 9% A = -40°C to +125°C rre rren 8% cu u c 7% 15% cc O 6% O 5% e of of 10% 4% ge tag 3% ta 2% 5% ercen 1% P ercen 0% P 0 4 8 2 6 0 4 8 0% -2.8 -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0. 0. 0. 1. 1. 2. 2. 2. 0 -8 -6 -4 -2 0 2 4 6 8 -1 10 Input Offset Voltage (mV) Input Offset Voltage Drift (µV/°C) FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage Drift.
30% 40% 210 Samples 210 Samples T es 35% A = +125°C T 25% A = 85°C ces nc 30% rre 20% rren cu 25% 15% Oc 20% f Occu of 10% 15% e o tage tag 10% 5% en en c 5% rc 0% Per Pe 0 0% 200 400 600 800 0 10 20 30 40 50 60 70 80 90 100 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 Input Bias Current (pA) Input Bias Current (pA) FIGURE 2-2:
Input Bias Current at
FIGURE 2-5:
Input Bias Current at T T A = +85 °C. A = +125 °C.
400 800 V V DD = 5.5V DD = 2.4V 750 ) 350 V 700 µ 650 T 300 A = +125°C 600 TA = +85°C 250 550 TA = +25°C 500 TA = -40°C 200 Voltage (µV) t Voltage ( T 450 A = -40°C 150 T ffse A = +25°C 400 T O 350 t Offset 100 A = +85°C T 300 pu A = +125°C 50 Input In 250 200 0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-3:
Input Offset Voltage vs.
FIGURE 2-6:
Input Offset Voltage vs. Common Mode Input Voltage at V Common Mode Input Voltage at V DD = 2.4V. DD = 5.5V. © 2007 Microchip Technology Inc. DS21812E-page 5 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the Chip Select (CS) pin on the MCP6293 and MCP6295. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Bias Current at TA = +85 ˚C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 2.4V. FIGURE 2-4: Input Offset Voltage Drift. FIGURE 2-5: Input Bias Current at TA = +125 ˚C. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: CMRR, PSRR vs. Frequency. FIGURE 2-9: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +85˚C. FIGURE 2-10: Input Bias, Input Offset Currents vs. Ambient Temperature. FIGURE 2-11: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-12: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +125˚C. FIGURE 2-13: Quiescent Current vs. Power Supply Voltage. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-16: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-17: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-18: Slew Rate vs. Ambient Temperature. FIGURE 2-19: Input Noise Voltage Density vs. Frequency. FIGURE 2-20: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-21: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 2.4V (MCP6293 and MCP6295 only). FIGURE 2-22: Input Noise Voltage Density vs. Common Mode Input Voltage at 10 kHz. FIGURE 2-23: Channel-to-Channel Separation vs. Frequency (MCP6292, MCP6294 and MCP6295 only). FIGURE 2-24: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 5.5V (MCP6293 and MCP6295 only). FIGURE 2-25: Large-Signal Non-inverting Pulse Response. FIGURE 2-26: Small-Signal Non-inverting Pulse Response. FIGURE 2-27: Chip Select (CS) to Amplifier Output Response Time at VDD = 2.4V (MCP6293 and MCP6295 only). FIGURE 2-28: Large-Signal Inverting Pulse Response. FIGURE 2-29: Small-Signal Inverting Pulse Response. FIGURE 2-30: Chip Select (CS) to Amplifier Output Response Time at VDD = 5.5V (MCP6293 and MCP6295 only). FIGURE 2-31: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-32: The MCP6291/1R/2/3/4/5 Show No Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 MCP6295’s VOUTA/VINB+ Pin 3.4 Chip Select Digital Input 3.5 Power Supply Pins 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.4 MCP629X Chip Select 4.5 Cascaded Dual Op Amps (MCP6295) FIGURE 4-5: Cascaded Gain Amplifier. 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-8: Multiple Feedback Low- Pass Filter. FIGURE 4-9: Photodiode Amplifier. FIGURE 4-10: Isolating the Load with a Buffer. FIGURE 4-11: Cascaded Gain Circuit Configuration. FIGURE 4-12: Difference Amplifier Circuit. FIGURE 4-13: Buffered Non-inverting Integrator with Chip Select. FIGURE 4-14: Integrator Circuit with Active Compensation. FIGURE 4-15: Second-Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair. FIGURE 4-16: Second-Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select. FIGURE 4-17: Capacitorless Second-Order Low-Pass Filter with Chip Select. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Simulator Tool 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, and CS is tied low.
12% 25% 11% es 840 Samples c es 840 Samples V 10% V CM = VSS n CM = VSS c 20% T 9% A = -40°C to +125°C rre rren 8% cu u c 7% 15% cc O 6% O 5% e of of 10% 4% ge tag 3% ta 2% 5% ercen 1% P ercen 0% P 0 4 8 2 6 0 4 8 0% -2.8 -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0. 0. 0. 1. 1. 2. 2. 2. 0 -8 -6 -4 -2 0 2 4 6 8 -1 10 Input Offset Voltage (mV) Input Offset Voltage Drift (µV/°C) FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
Input Offset Voltage Drift.
30% 40% 210 Samples 210 Samples T es 35% A = +125°C T 25% A = 85°C ces nc 30% rre 20% rren cu 25% 15% Oc 20% f Occu of 10% 15% e o tage tag 10% 5% en en c 5% rc 0% Per Pe 0 0% 200 400 600 800 0 10 20 30 40 50 60 70 80 90 100 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 Input Bias Current (pA) Input Bias Current (pA) FIGURE 2-2:
Input Bias Current at
FIGURE 2-5:
Input Bias Current at T T A = +85 °C. A = +125 °C.
400 800 V V DD = 5.5V DD = 2.4V 750 ) 350 V 700 µ 650 T 300 A = +125°C 600 TA = +85°C 250 550 TA = +25°C 500 TA = -40°C 200 Voltage (µV) t Voltage ( T 450 A = -40°C 150 T ffse A = +25°C 400 T O 350 t Offset 100 A = +85°C T 300 pu A = +125°C 50 Input In 250 200 0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Common Mode Input Voltage (V) Common Mode Input Voltage (V) FIGURE 2-3:
Input Offset Voltage vs.
FIGURE 2-6:
Input Offset Voltage vs. Common Mode Input Voltage at V Common Mode Input Voltage at V DD = 2.4V. DD = 5.5V. © 2007 Microchip Technology Inc. DS21812E-page 5 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the Chip Select (CS) pin on the MCP6293 and MCP6295. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Bias Current at TA = +85 ˚C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 2.4V. FIGURE 2-4: Input Offset Voltage Drift. FIGURE 2-5: Input Bias Current at TA = +125 ˚C. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: CMRR, PSRR vs. Frequency. FIGURE 2-9: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +85˚C. FIGURE 2-10: Input Bias, Input Offset Currents vs. Ambient Temperature. FIGURE 2-11: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-12: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +125˚C. FIGURE 2-13: Quiescent Current vs. Power Supply Voltage. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-16: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-17: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-18: Slew Rate vs. Ambient Temperature. FIGURE 2-19: Input Noise Voltage Density vs. Frequency. FIGURE 2-20: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-21: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 2.4V (MCP6293 and MCP6295 only). FIGURE 2-22: Input Noise Voltage Density vs. Common Mode Input Voltage at 10 kHz. FIGURE 2-23: Channel-to-Channel Separation vs. Frequency (MCP6292, MCP6294 and MCP6295 only). FIGURE 2-24: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 5.5V (MCP6293 and MCP6295 only). FIGURE 2-25: Large-Signal Non-inverting Pulse Response. FIGURE 2-26: Small-Signal Non-inverting Pulse Response. FIGURE 2-27: Chip Select (CS) to Amplifier Output Response Time at VDD = 2.4V (MCP6293 and MCP6295 only). FIGURE 2-28: Large-Signal Inverting Pulse Response. FIGURE 2-29: Small-Signal Inverting Pulse Response. FIGURE 2-30: Chip Select (CS) to Amplifier Output Response Time at VDD = 5.5V (MCP6293 and MCP6295 only). FIGURE 2-31: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-32: The MCP6291/1R/2/3/4/5 Show No Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 MCP6295’s VOUTA/VINB+ Pin 3.4 Chip Select Digital Input 3.5 Power Supply Pins 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.4 MCP629X Chip Select 4.5 Cascaded Dual Op Amps (MCP6295) FIGURE 4-5: Cascaded Gain Amplifier. 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-8: Multiple Feedback Low- Pass Filter. FIGURE 4-9: Photodiode Amplifier. FIGURE 4-10: Isolating the Load with a Buffer. FIGURE 4-11: Cascaded Gain Circuit Configuration. FIGURE 4-12: Difference Amplifier Circuit. FIGURE 4-13: Buffered Non-inverting Integrator with Chip Select. FIGURE 4-14: Integrator Circuit with Active Compensation. FIGURE 4-15: Second-Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair. FIGURE 4-16: Second-Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select. FIGURE 4-17: Capacitorless Second-Order Low-Pass Filter with Chip Select. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Simulator Tool 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information