Datasheet MCP6291, MCP6291R, MCP6292, MCP6293, MCP6294, MCP6295 (Microchip) - 2

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MCP6291/1R/2/3/4/5 1.0 ELECTRICAL † Notice:
Stresses above those listed under “Absolute
CHARACTERISTICS
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those
Absolute Maximum Ratings †
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended VDD – VSS ..7.0V periods may affect device reliability. Current at Input Pins ...±2 mA
††
See
Section 4.1.2 “Input Voltage and Current Limits”
. Analog Inputs (VIN+, VIN–) †† .. VSS – 1.0V to VDD + 1.0V All Other Inputs and Outputs ... VSS – 0.3V to VDD + 0.3V Difference Input Voltage .. |VDD – VSS| Output Short Circuit Current ...Continuous Current at Output and Supply Pins ..±30 mA Storage Temperature.. –65°C to +150°C Maximum Junction Temperature (TJ) ..+150°C ESD Protection On All Pins (HBM; MM) .. ≥ 4 kV; 400V
DC ELECTRICAL SPECIFICATIONS Electrical Characteristics
: Unless otherwise indicated, T ≈ A = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VOUT VDD/2, VCM = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions Input Offset
Input Offset Voltage VOS -3.0 — +3.0 mV VCM = VSS
(Note 1 )
Input Offset Voltage VOS -5.0 — +5.0 mV TA = -40°C to +125°C, (Extended Temperature) VCM = VSS
(Note 1 )
Input Offset Temperature Drift ΔVOS/ΔTA — ±1.7 — µV/°C TA = -40°C to +125°C, V
(Note 1 )
CM = VSS Power Supply Rejection Ratio PSRR 70 90 — dB V
(Note 1 )
CM = VSS
Input Bias, Input Offset Current and Impedance
Input Bias Current IB — ±1.0 — pA
Note 2
At Temperature IB — 50 200 pA TA = +85°C
(Note 2)
At Temperature IB — 2 5 nA TA = +125°C
(Note 2 )
Input Offset Current IOS — ±1.0 — pA
Note 3
Common Mode Input Impedance ZCM — 1013||6 — Ω||pF
Note 3
Differential Input Impedance ZDIFF — 1013||3 — Ω||pF
Note 3 Common Mode (Note 4)
Common Mode Input Range V − CMR VSS 0.3 — VDD + 0.3 V Common Mode Rejection Ratio CMRR 70 85 — dB VCM = -0.3V to 2.5V, VDD = 5V Common Mode Rejection Ratio CMRR 65 80 — dB VCM = -0.3V to 5.3V, VDD = 5V
Open-Loop Gain
DC Open-Loop Gain (Large Signal) AOL 90 110 — dB VOUT = 0.2V to VDD – 0.2V, VCM = VSS
(Note 1) Output
Maximum Output Voltage Swing VOL, VOH VSS + 15 — VDD – 15 mV 0.5V Input Overdrive Output Short Circuit Current ISC — ±25 — mA
Power Supply
Supply Voltage VDD 2.4 — 6.0 V TA = -40°C to +125°C
(Note 5 )
Quiescent Current per Amplifier IQ 0.7 1.0 1.3 mA IO = 0
Note 1:
The MCP6295’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.
2:
The current at the MCP6295’s VINB– pin is specified by IB only.
3:
This specification does not apply to the MCP6295’s VOUTA/VINB+ pin.
4:
The MCP6295’s VINB– pin (op amp B) has a common mode range (VCMR) of VSS + 100 mV to VDD – 100 mV. The MCP6295’s VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL.
5:
All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However, the other minimum and maximum specifications are measured at 2.4V and or 5.5V. DS21812E-page 2 © 2007 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the Chip Select (CS) pin on the MCP6293 and MCP6295. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Bias Current at TA = +85 ˚C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 2.4V. FIGURE 2-4: Input Offset Voltage Drift. FIGURE 2-5: Input Bias Current at TA = +125 ˚C. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: CMRR, PSRR vs. Frequency. FIGURE 2-9: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +85˚C. FIGURE 2-10: Input Bias, Input Offset Currents vs. Ambient Temperature. FIGURE 2-11: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-12: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +125˚C. FIGURE 2-13: Quiescent Current vs. Power Supply Voltage. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-16: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-17: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-18: Slew Rate vs. Ambient Temperature. FIGURE 2-19: Input Noise Voltage Density vs. Frequency. FIGURE 2-20: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-21: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 2.4V (MCP6293 and MCP6295 only). FIGURE 2-22: Input Noise Voltage Density vs. Common Mode Input Voltage at 10 kHz. FIGURE 2-23: Channel-to-Channel Separation vs. Frequency (MCP6292, MCP6294 and MCP6295 only). FIGURE 2-24: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 5.5V (MCP6293 and MCP6295 only). FIGURE 2-25: Large-Signal Non-inverting Pulse Response. FIGURE 2-26: Small-Signal Non-inverting Pulse Response. FIGURE 2-27: Chip Select (CS) to Amplifier Output Response Time at VDD = 2.4V (MCP6293 and MCP6295 only). FIGURE 2-28: Large-Signal Inverting Pulse Response. FIGURE 2-29: Small-Signal Inverting Pulse Response. FIGURE 2-30: Chip Select (CS) to Amplifier Output Response Time at VDD = 5.5V (MCP6293 and MCP6295 only). FIGURE 2-31: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-32: The MCP6291/1R/2/3/4/5 Show No Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 MCP6295’s VOUTA/VINB+ Pin 3.4 Chip Select Digital Input 3.5 Power Supply Pins 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.4 MCP629X Chip Select 4.5 Cascaded Dual Op Amps (MCP6295) FIGURE 4-5: Cascaded Gain Amplifier. 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-8: Multiple Feedback Low- Pass Filter. FIGURE 4-9: Photodiode Amplifier. FIGURE 4-10: Isolating the Load with a Buffer. FIGURE 4-11: Cascaded Gain Circuit Configuration. FIGURE 4-12: Difference Amplifier Circuit. FIGURE 4-13: Buffered Non-inverting Integrator with Chip Select. FIGURE 4-14: Integrator Circuit with Active Compensation. FIGURE 4-15: Second-Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair. FIGURE 4-16: Second-Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select. FIGURE 4-17: Capacitorless Second-Order Low-Pass Filter with Chip Select. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Simulator Tool 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information