Datasheet MCP6281, MCP6281R, MCP6282, MCP6283, MCP6284, MCP6285 (Microchip)

MCP6281/1R/2/3/4/5 450 µA, 5 MHz Rail-to-Rail Op Amp Features Description
• Gain Bandwidth Product: 5 MHz (typical) The Microchip Technology Inc. MCP6281/1R/2/3/4/5 • Supply Current: I family of operational amplifiers (op amps) provide wide Q = 450 µA (typical) • Supply Voltage: 2.2V to 6.0V bandwidth for the current. This family has a 5 MHz Gain Bandwidth Product (GBWP) and a 65° phase margin. • Rail-to-Rail Input/Output This family also operates from a single supply voltage • Extended Temperature Range: -40°C to +125°C as low as 2.2V, while drawing 450 µA (typical) quiescent • Available in Single, Dual, and Quad Packages current. Additionally, the MCP6281/1R/2/3/4/5 supports • Single with CS (
MCP6283
) rail-to-rail input and output swing, with a common mode • Dual with CS (
MCP6285
) input voltage range of VDD + 300 mV to VSS – 300 mV. This family of operational amplifiers is designed with
Applications
Microchip’s advanced CMOS process. The MCP6285 has a Chip Select (CS) input for dual op • Automotive amps in an 8-pin package. This device is manufactured • Portable Equipment by cascading the two op amps (the output of op amp A • Photodiode Amplifier connected to the non-inverting input of op amp B). The • Analog Filters CS input puts the device in Low-power mode. • Notebooks and PDAs The MCP6281/1R/2/3/4/5 family operates over the • Battery-Powered Systems Extended Temperature Range of -40°C to +125°C. It also has a power supply range of 2.2V to 6.0V.
Design Aids
• SPICE Macro Models • FilterLab® Software • Mindi™ Circuit Designer & Simulator • MAPS (Microchip Advanced Part Selector) • Analog Demonstration and Evaluation Boards • Application Notes
Package Types MCP6281 MCP6281 MCP6281R MCP6282
PDIP, SOIC, MSOP PDIP, SOIC, MSOP SOT-23-5 SOT-23-5 NC 1 8 NC VOUTA 1 8 VDD VOUT 1 5 VDD VOUT 1 5 VSS V _ _ IN 2 - 7 VDD V 2 INA - + 7 VOUTB VSS 2 + VDD 2 + V - - IN+ 3 + 6 VOUT V 3 + _ INA+ - 6 VINB VIN+ 3 4 VIN– VIN+ 3 4 VIN– VSS 4 5 NC VSS 4 5 VINB+
MCP6283 MCP6283 MCP6284 MCP6285
PDIP, SOIC, MSOP SOT-23-6 PDIP, SOIC, TSSOP PDIP, SOIC, MSOP NC 1 8 CS VOUTA 1 14 VOUTD V V V 1 6 DD OUTA/VINB+ 1 8 VDD V _ OUT _ IN 2 - 7 VDD V 2 _ INA - + + - 13 VIND VSS 2 + 5 CS V _ 2 - + 7 V V INA OUTB - IN+ 3 + 6 VOUT V 3 12 _ INA+ VIND+ V V IN+ 3 4 V _ IN 3 + - 6 V V INA+ INB SS 4 5 NC V 4 11 DD VSS VSS 4 5 CS V 5 10 INB+ VINC+ V _ _ INB 6 - + + - 9 VINC VOUTB 7 8 VOUTC © 2008 Microchip Technology Inc. DS21811E-page 1 Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the Chip Select (CS) pin on the MCP6283 and MCP6285. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Bias Current at TA = +85 ˚C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 2.2V. FIGURE 2-4: Input Offset Voltage Drift. FIGURE 2-5: Input Bias Current at TA = +125 ˚C. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: CMRR, PSRR vs. Frequency. FIGURE 2-9: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +85˚C. FIGURE 2-10: Input Bias, Input Offset Currents vs. Ambient Temperature. FIGURE 2-11: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-12: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +125˚C. FIGURE 2-13: Quiescent Current vs. Power Supply Voltage. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-16: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-17: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-18: Slew Rate vs. Ambient Temperature. FIGURE 2-19: Input Noise Voltage Density vs. Frequency. FIGURE 2-20: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-21: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 2.2V (MCP6283 and MCP6285 only). FIGURE 2-22: Input Noise Voltage Density vs. Common Mode Input Voltage at 1 kHz. FIGURE 2-23: Channel-to-Channel Separation vs. Frequency (MCP6282 and MCP6284 only). FIGURE 2-24: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 5.5V (MCP6283 and MCP6285 only). FIGURE 2-25: Large-Signal, Non-inverting Pulse Response. FIGURE 2-26: Small-Signal, Non-inverting Pulse Response. FIGURE 2-27: Chip Select (CS) to Amplifier Output Response Time at VDD = 2.2V (MCP6283 and MCP6285 only). FIGURE 2-28: Large-Signal, Inverting Pulse Response. FIGURE 2-29: Small-Signal, Inverting Pulse Response. FIGURE 2-30: Chip Select (CS) to Amplifier Output Response Time at VDD = 5.5V (MCP6283 and MCP6285 only). FIGURE 2-31: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-32: The MCP6281/1R/2/3/4/5 Show No Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 MCP6285’s VOUTA/VINB+ Pin 3.4 Chip Select Digital Input (CS) 3.5 Power Supply Pins 4.0 Application infoRmation 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.4 MCP628X Chip Select (CS) 4.5 Cascaded Dual Op Amps (MCP6285) FIGURE 4-5: Cascaded Gain Amplifier. 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-8: Sallen-Key High-Pass Filter. FIGURE 4-9: Miller Integrator. FIGURE 4-10: Isolating the Load with a Buffer. FIGURE 4-11: Cascaded Gain Circuit Configuration. FIGURE 4-12: Difference Amplifier Circuit. FIGURE 4-13: Buffered Non-inverting Integrator with Chip Select. FIGURE 4-14: Integrator Circuit with Active Compensation. FIGURE 4-15: Second-Order Multiple Feedback Low-Pass Filter with an Extra Pole-Zero Pair. FIGURE 4-16: Second-Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select. FIGURE 4-17: Capacitorless Second-Order Low-Pass Filter with Chip Select. 5.0 Design AIDS 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information