Datasheet MCP6001, MCP6001R, MCP6001U, MCP6002, MCP6004 (Microchip) - 8

MCP6001/1R/1U/2/4 Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 kΩ to VL, and CL = 60 pF.
14% 100
1230 Samples VCM = VSS
12%
VDD = 5.5V
90
VCM = VDD
10%
T
80
A = +85°C
70 8% Occurrences RR (dB)
PSRR–
60 6%
PSRR+
50 age of 4%
CMRR
40 PSRR, CM 2% 30 Percent 0% 20 0 3 6 9 12 15 18 21 24 27 30 1.E+0 10 1 1.E+ 10002 1.E+03 1k 1.E+ 10 04 k 1.E+ 10 05 0k Input Bias Current (pA) Frequency (Hz) FIGURE 2-7:
Input Bias Current at +85°C.
FIGURE 2-10:
PSRR, CMRR vs. Frequency.
55% 120 0 50%
605 Samples V
45%
DD = 5.5V
100 -30
V
40%
CM = VDD
°)
T
35%
A = +125°C
80 -60
Phase
ase ( 30% 60 -90 h 25% 20% 40 -120 age of Occurrences 15%
Gain
Loop P 10% 20 -150 5% Open-Loop Gain (dB) Open- Percent 0 -180 0%
VCM = VSS
0 0 0 0 0 0 0 -20 -210 15 30 45 60 75 90 50 00 50 00 10 12 13 15 1.0E . - 1 1.E1+ 1.E+ 10 1.1E 0 + 0 1.E+ 1k 1.E 1 + 0k 1.E 10 + 0k 1.E+ 1M 1. 1 E 0 + M Input Bias Current (pA) 01 00 01 02 03 Frequency 04 (Hz) 05 06 07 FIGURE 2-8:
Input Bias Current at
FIGURE 2-11:
Open-Loop Gain, Phase vs. +125°C. Frequency.
100 1,000
VDD = 5.0V
95 B) d 90
PSRR (VCM = VSS)
Hz) 85 /
√
100 V (n 80 PSRR, CMRR (
CMRR (V
75
CM = -0.3V to +5.3V)
Input Noise Voltage Density 70 10 -50 -25 0 25 50 75 100 125 1.E-0 0.1 1 1.E+ 1 0 1.E 1 + 0 0 1.E 1 + 0 0 0 1.E 1 + k 0 1.E+0 10k 1.E 10 +0 0k Ambient Temperature (°C) 0 1 2 Frequency (H 3 z) 4 5 FIGURE 2-9:
CMRR, PSRR vs. Ambient
FIGURE 2-12:
Input Noise Voltage Density Temperature. vs. Frequency. DS21733J-page 8 © 2009 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics 1.1 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Quadratic Temp. Co. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Output Voltage. FIGURE 2-7: Input Bias Current at +85°C. FIGURE 2-8: Input Bias Current at +125°C. FIGURE 2-9: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-10: PSRR, CMRR vs. Frequency. FIGURE 2-11: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-12: Input Noise Voltage Density vs. Frequency. FIGURE 2-13: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-15: Quiescent Current vs. Power Supply Voltage. FIGURE 2-16: Small-Signal, Non-Inverting Pulse Response. FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response. FIGURE 2-18: Slew Rate vs. Ambient Temperature. FIGURE 2-19: Output Voltage Swing vs. Frequency. FIGURE 2-20: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-21: The MCP6001/2/4 Show No Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-7: Instrumentation Amplifier with Unity-Gain Buffer Inputs. FIGURE 4-8: Active Second-Order Low-Pass Filter. FIGURE 4-9: Peak Detector with Clear and Sample CMOS Analog Switches. 5.0 Design AIDS 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information