Datasheet MCP6231, MCP6231R, MCP6231U, MCP6232, MCP62314 (Microchip)

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MCP6231/1R/1U/2/4 20 µA, 300 kHz Rail-to-Rail Op Amp Features Description
• Gain Bandwidth Product: 300 kHz (typical) The Microchip Technology Inc. MCP6231/1R/1U/2/4 • Supply Current: I operational amplifiers (op amps) provide wide Q = 20 µA (typical) bandwidth for the quiescent current. The MCP6231/1R/ • Supply Voltage: 1.8V to 6.0V 1U/2/4 family has a 300 kHz gain bandwidth product • Rail-to-Rail Input/Output and 65°C (typical) phase margin. This family operates • Extended Temperature Range: -40°C to +125°C from a single supply voltage as low as 1.8V, while • Available in 5-Pin SC70 and SOT-23 packages drawing 20 µA (typical) quiescent current. In addition, the MCP6231/1R/1U/2/4 family supports rail-to-rail
Applications
input and output swing, with a common mode input voltage range of VDD + 300 mV to VSS – 300 mV. • Automotive These op amps are designed in one of Microchip’s • Portable Equipment advanced CMOS processes. • Transimpedance amplifiers
Package Types
• Analog Filters
MCP6231 MCP6231
• Notebooks and PDAs SOT-23-5 MSOP, PDIP, SOIC • Battery-Powered Systems V NC 1 8 NC OUT OU 1 5 V 5 DD
Design Aids
V V 2 – 7 VDD SS 2 + IN– – 3 + 6 V V V 3 4 V IN+ OUT • SPICE Macro Models IN+ 3 4 IN– VSS 4 5 NC • FilterLab® Software
MCP6232
• Mindi™ Circuit Designer & Simulator
MCP6231R
• Microchip Advanced Part Selector (MAPS) SOT-23-5 MSOP, PDIP, SOIC • Analog Demonstration and Evaluation Boards V V OUT 1 5 VSS OUTA 1 8 VDD • Application Notes V _ DD 2 + V 2 INA - + 7 V – OUTB V _ IN+ 3 4 VIN– V 3 + INA+ - 6 V
Typical Application
INB VSS 4 5 VINB+ RG2
MCP6231U MCP6232
VIN2 SC70-5, SOT-23-5 2x3 TDFN * RG1 V 1 8 V OUTA DD V VIN+ 1 5 VDD IN1 R + F V _ 2 EP 7 V V INA OUTB SS 2 V – 9 _ DD V 3 6 V
–
V INA+ INB IN– 3 4 VOUT V 4 5 V R SS INB+ X
MCP6231
VOUT
MCP6231 + MCP6234
R DFN * Y R PDIP, SOIC, TSSOP Z NC 1 8 NC V 1 14 OUTA VOUTD V 2 EP 7 V V IN– DD INA– 2 - + + - 13 VIND– 9 V V 3 6 V INA+ 3 12 VIND+ IN+ OUT V V 4 5 NC DD 4 11 V
Summing Amplifier Circuit
SS SS V 5 10 INB+ VINC+ V 6 - + + - 9 INB– VINC– V 7 8 OUTB VOUTC * Includes Exposed Thermal Pad (EP); see Table 3-1. © 2009 Microchip Technology Inc. DS21881E-page 1 Document Outline 1.0 Electrical Characteristics 1.1 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-2: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: PSRR, CMRR vs. Frequency. FIGURE 2-3: Input Bias Current at +85°C. FIGURE 2-4: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-5: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-6: Input Bias Current at +125°C. FIGURE 2-7: Input Noise Voltage Density vs. Frequency. FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-10: Input Offset Voltage Drift. FIGURE 2-11: Input Offset Voltage vs. Output Voltage. FIGURE 2-12: Output Short-Circuit Current vs. Ambient Temperature. FIGURE 2-13: Slew Rate vs. Ambient Temperature. FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-16: Small-Signal, Non-Inverting Pulse Response. FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response. FIGURE 2-18: Quiescent Current vs. Power Supply Voltage. FIGURE 2-19: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-20: The MCP6231/1R/1U/2/4 Show No Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply (VSS and VDD) 3.4 Exposed Thermal Pad (EP) 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: The MCP6231/1R/1U/2/4 Show No Phase Reversal. FIGURE 4-2: Simplified Analog Input ESD Structures. FIGURE 4-3: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output resistor, RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-8: Summing Amplifier Circuit. FIGURE 4-9: Effect of Parasitic Capacitance at the Input. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information