Datasheet LMC7101 (Microchip) - 9

LMC7101 Micrel, Inc.
Application Information
0
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V 011 R 8 8
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9 OUT = = ≈ Ω
Input Common-Mode Voltage
0 001245
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A Some amplifiers exhibit undesirable or unpredictable perfor-
Driving Capacitive Loads
mance when the inputs are driven beyond the common-mode Driving a capacitive load introduces phase-lag into the output voltage range, for example, phase inversion of the output signal, and this in turn reduces op-amp system phase margin. signal. The LMC7101 tolerates input overdrive by at least The application that is least forgiving of reduced phase 200mV beyond either rail without producing phase inversion. margin is a unity gain amplifier. The LMC7101 can typically If the absolute maximum input voltage (700mV beyond either drive a 100pF capacitive load connected directly to the output rail) is exceeded, the input current should be limited to ±5mA when configured as a unity-gain amplifier. maximum to prevent reducing reliability. A 10kΩ series input
Using Large-Value Feedback Resistors
resistor, used as a current limiter, will protect the input A large-value feedback resistor (> 500kΩ) can reduce the structure from voltages as large as 50V above the supply or phase margin of a system. This occurs when the feedback below ground. See Figure 1. resistor acts in conjunction with input capacitance to create phase lag in the fedback signal. Input capacitance is usually a combination of input circuit components and other parasitic capacitance, such as amplifier input capacitance and stray printed circuit board capacitance. VOUT RIN V Figure 2 illustrates a method of compensating phase lag IN 10kΩ caused by using a large-value feedback resistor. Feedback capacitor C introduces sufficient phase lead to overcome FB
Figure 1. Input Current-Limit Protection
the phase lag caused by feedback resistor R and input FB capacitance C . The value of C is determined by first IN FB
Output Voltage Swing
estimating C and then applying the following formula: IN Sink and source output resistances of the LMC7101 are R × C ≤ R × C equal. Maximum output voltage swing is determined by the IN IN FB FB load and the approximate output resistance. The output CFB resistance is: RFB V R = DROP OUT I RIN LOAD VIN V is the voltage dropped within the amplifier output V DROP OUT stage. V and I can be determined from the V C DROP LOAD O IN (output swing) portion of the appropriate Electrical Character- istics table. I is equal to the typical output high voltage LOAD minus V+/2 and divided by R . For example, using the LOAD Electrical Characteristics DC (5V) table, the typical output
Figure 2. Cancelling Feedback Phase Lag
high voltage using a 2kΩ load (connected to V+/2) is 4.989V, Since a significant percentage of C may be caused by board which produces an I of IN LOAD layout, it is important to note that the correct value of C may FB  4 989
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V – 2 5
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V  change when changing from a breadboard to the final circuit 1 245
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mA   = 1 245
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mA .  layout. 2kΩ  Voltage drop in the amplifier output stage is: V = 5.0V – 4.989V DROP V = 0.011V DROP Because of output stage symmetry, the corresponding typical output low voltage (0.011V) also equals V . Then: DROP February 2005 9 LMC7101