Datasheet LTC1041 (Analog Devices) - 6

LTC1041
U U W U APPLICATIO S I FOR ATIO
V+ In applications where an absolute reference is required, 8 the VP-P output can be used to drive a fast settling reference. The LTC1009 2.5V reference settles in ≈ 2µs Q1 P1 and is ideal for this application (Figure 5). The current through R1 must be large enough to supply the LT1009 80µs COMPARATOR ON TIME minimum bias current (≈ 1mA) and the load current, IL. 4 7 GND VP-P LTC1041 • AI03
Internal Oscillator Figure 3. VP-P Output Switch
An internal oscillator allows the LTC1041 to strobe itself. The frequency of the oscillation, and hence the sampling rate, is set with an external RC network (see typical curve, V+ Sampling Rate REXT, CEXT). REXT and CEXT are connected R1 as shown in Figure 1. To assure oscillation, R 1 8 EXT must be R3 R5 V between 100kΩ and 10MΩ. There is no limit to the size of IN 2 7 VP-P R4 R6 SET POINT 3 LTC1041 6 CEXT. GND 4 5 DELTA R2 At low sampling rates, REXT is very important in determining the power consumption. REXT consumes power continuously. The average voltage at the OSC pin is approximately V+/2, giving a power dissipation of LTC1041 • AI04 PREXT = (V+/ 2)2/REXT.
Figure 4. Ratiometric Network Driven by VP-P
Example: assume REXT = 1MΩ, V+ = 5V, PREXT = (2.5)2/106 = 6.25/µW. This is approximately four times the V+ power consumed by the LTC1041 at V+ = 5V and R1 1 8 fS = 1 sample/second. Where power is a premium, 2 7 I R L R2 VIN EXT should be made as large as possible. Note that the SET POINT 3 LTC1041 6 power dissipated by REXT is not a function of fS or CEXT. 4 5 DELTA R3 If high sampling rates are needed and power consumption LT1009-2.5 is of secondary importance, a convenient way to get the R4 maximum possible sampling rate is to make REXT = 100kΩ LTC1041 • AI05 and CEXT = 0. The sampling rate, set by the controller’s
Figure 5. Driving Reference with V
active time, will nominally be ≈ 10kHz.
P-P Output
To synchronize the Sampling of the LTC1041 to an If the best possible performance is needed, the inputs to external frequency source, the OSC pin can be driven by a the LTC1041 must completely settle within 4µs of the start CMOS gate. A CMOS gate is necessary because the input of the comparison cycle (VP-P high impedance to V+ trip points of the oscillator are close to the supply rails and transition). Also, it is critical that the input voltages do not TTL does not have enough output swing. Externally driven, change during the 80µs active time. When driving resistive there will be a delay from the rising edge of the OSC input input networks with VP-P, capacitive loading should be and the start of the sampling cycle of approximately 5µs. minimized to meet the 4µs settling time requirement. Further, care should be exercised in layout when driving networks with source impedances, as seen by the LTC1041, of greater than 10kΩ (see For RS > 10kΩ). 1041fa 6