Datasheet LTC1040 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | Dual Micropower Comparator |
| Páginas / Página | 12 / 6 — APPLICATIO S I FOR ATIO. Minimizing Comparison Errors. Tracking Error. … |
| Formato / tamaño de archivo | PDF / 227 Kb |
| Idioma del documento | Inglés |
APPLICATIO S I FOR ATIO. Minimizing Comparison Errors. Tracking Error. (a) OK. (b) Optimum. Figure 3. Two Ways to Do It
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LTC1040
U U W U APPLICATIO S I FOR ATIO Minimizing Comparison Errors Tracking Error
The two differential input voltages, V1 and V2, are con- Tracking error is caused by the ratio error between CIN1 verted to charge by the input capacitors C and C IN1 and CIN2 (see IN2 and is expressed as a percentage. For example, Figure 2). The charge is summed at the virtual ground consider Figure 3a with VREF = 1V. Then at null, point; if the net charge is positive, the comparator output is high and if negative, it is low. There is an optimum way C V IN1 IN = VREF = 1V ± 1mV to connect these inputs, in a specific application, to CIN2 minimize error. because CIN1 is guaranteed to equal CIN2 to within 0.1%. CIN1 VIRTUAL S1 GROUND + V1 VREF V + REF + S2 – VIN – – + + VIN – – CIN2 + V2
(a) OK (b) Optimum
–
Figure 3. Two Ways to Do It
LTC1040 • TA03 LTC1040 DUAL DIFFERENTIAL INPUT LTC1040 • AI02
Figure 2. Dual Differential Equivalent Input Circuit Common Mode Range
The input switches of the LTC1040 are capable of Ignoring internal offset, the LTC1040 will be at its switch- switching to either the V+ or V– supply. This means that the ing point when: input common mode range includes both supply rails. V1 • C Many applications, not feasible with conventional com- IN1 + V2 • CIN2 = 0. parators, are possible with the LTC1040. In the load Optimum error will be achieved when the differential current detector shown in Figure 4, a 0.1Ω resistor is used voltages, V1 and V2, are individually minimized. Figure 3 to sense the current in the V+ supply. This application shows two ways to connect the LTC1040 to compare an requires the dual differential input and common mode input voltage, VIN, to a reference voltage, VREF. Using the capabilities of the LTC1040. above equation, each method will be at null when: (a) (VREF – 0V) CIN1 – (0V – VIN) CIN2 = 0 or V I IN = VREF (CIN1/CIN2) L (b) (VREF – VIN) CIN1 – (0V – 0V) CIN2 = 0 0.1Ω or V RL – IN = VREF. + 1/2 OUT Notice that in method (a) the null point depends on the – + LTC1040 + ratio of C V 100mV IN1/CIN2, but method (b) is independent of this S ratio. Also, because method (b) has zero differential input voltage, the errors due to finite input resistance are OUT = HI IF IL > 1A negligible. The LTC1040 has a high accuracy capacitor OUT = LO IF IL < 1A array and even the non-optimum connection will only LTC1040 • AI04 result in ± 0.1% more error, worst-case compared to the
Figure 4. Load Current Detector
optimum connection. 1040fa 6
U U W U APPLICATIO S I FOR ATIO Minimizing Comparison Errors Tracking Error
The two differential input voltages, V1 and V2, are con- Tracking error is caused by the ratio error between CIN1 verted to charge by the input capacitors C and C IN1 and CIN2 (see IN2 and is expressed as a percentage. For example, Figure 2). The charge is summed at the virtual ground consider Figure 3a with VREF = 1V. Then at null, point; if the net charge is positive, the comparator output is high and if negative, it is low. There is an optimum way C V IN1 IN = VREF = 1V ± 1mV to connect these inputs, in a specific application, to CIN2 minimize error. because CIN1 is guaranteed to equal CIN2 to within 0.1%. CIN1 VIRTUAL S1 GROUND + V1 VREF V + REF + S2 – VIN – – + + VIN – – CIN2 + V2
(a) OK (b) Optimum
–
Figure 3. Two Ways to Do It
LTC1040 • TA03 LTC1040 DUAL DIFFERENTIAL INPUT LTC1040 • AI02
Figure 2. Dual Differential Equivalent Input Circuit Common Mode Range
The input switches of the LTC1040 are capable of Ignoring internal offset, the LTC1040 will be at its switch- switching to either the V+ or V– supply. This means that the ing point when: input common mode range includes both supply rails. V1 • C Many applications, not feasible with conventional com- IN1 + V2 • CIN2 = 0. parators, are possible with the LTC1040. In the load Optimum error will be achieved when the differential current detector shown in Figure 4, a 0.1Ω resistor is used voltages, V1 and V2, are individually minimized. Figure 3 to sense the current in the V+ supply. This application shows two ways to connect the LTC1040 to compare an requires the dual differential input and common mode input voltage, VIN, to a reference voltage, VREF. Using the capabilities of the LTC1040. above equation, each method will be at null when: (a) (VREF – 0V) CIN1 – (0V – VIN) CIN2 = 0 or V I IN = VREF (CIN1/CIN2) L (b) (VREF – VIN) CIN1 – (0V – 0V) CIN2 = 0 0.1Ω or V RL – IN = VREF. + 1/2 OUT Notice that in method (a) the null point depends on the – + LTC1040 + ratio of C V 100mV IN1/CIN2, but method (b) is independent of this S ratio. Also, because method (b) has zero differential input voltage, the errors due to finite input resistance are OUT = HI IF IL > 1A negligible. The LTC1040 has a high accuracy capacitor OUT = LO IF IL < 1A array and even the non-optimum connection will only LTC1040 • AI04 result in ± 0.1% more error, worst-case compared to the
Figure 4. Load Current Detector
optimum connection. 1040fa 6