Datasheet LT1719 (Analog Devices) - 9

LT1719
APPLICATIONS INFORMATION Power Supply Confi gurations (SO-8 Package)
2.7V TO 6V 5V The LT1719S8 has separate supply pins for the input and VCC VCC 3V output stages that allow fl exible operation, accommodating + + +VS +VS separate voltage ranges for the analog input and the output LT1719S8 LT1719S8 GND GND logic. Of course, a single 3V/5V supply may be used by – – tying + VS and VCC together as well as GND and VEE. VEE VEE –5V The minimum voltage requirement can be simply stated as both the output and the input stages need at least 2.7V
Single Supply ±5VIN, 3VOUT
and the VEE pin must be equal to or less than ground. 10V The following rules must be adhered to in any VCC 5V VCC 3V confi guration: + + +VS +VS LT1719S8 LT1719S8 2.7V ≤ (VCC – VEE) ≤ 10.5V GND GND – – 2.7V ≤ (+ VS – GND) ≤ 6V VEE VEE (+VS – VEE) ≤ 10.5V –5.2V 1719 F01
10V
V
IN, 5VOUT Front End Entirely Negative
EE ≤ Ground Although the ground pin need not be tied to system ground,
Figure 1. Variety of SO-8 Power Supply Confi gurations
most applications will use it that way. Figure 1 shows three When either input signal falls below the negative com- common confi gurations. The fi nal one is uncommon, but mon mode limit, the internal PN diode formed with the it will work and may be useful as a level translator; the substrate can turn on, resulting in signifi cant current input stage is run from – 5.2V and ground while the output fl ow through the die. An external Schottky clamp diode stage is run from 3V and ground. In this case the com- between the input and the negative rail can speed up re- mon mode input voltage range does not include ground, covery from negative overdrive by preventing the substrate so it may be helpful to tie VCC to 3V anyway. Conversely, diode from turning on. VCC may also be tied below ground, as long as the above rules are not violated. When both input signals are below the negative common mode limit, phase reversal protection circuitry prevents
Input Voltage Considerations
false output inversion to at least – 400mV common mode. However, the offset and hysteresis in this mode will increase The LT1719 is specifi ed for a common mode range of dramatically, to as much as 15mV each. The input bias –100mV to 3.8V when used with a single 5V supply. A currents will also increase. more general consideration is that the common mode range is 100mV below VEE/V– to 1.2V below VCC/V+. The When both input signals are above the positive common criterion for this common mode limit is that the output still mode limit, the input stage will get debiased and the output responds correctly to a small differential input signal. If polarity will be random. However, the internal hysteresis one input is within the common mode limit, the other will hold the output to a valid logic level. When at least one input signal can go outside the common mode limits, up of the inputs returns to within the common mode limits, to the absolute maximum limits, and the output will retain recovery from this state can take as long as 1μs. the correct polarity. 1719fa 9