LT1116 applicaTions inForMaTionInput CharacteristicsLatch Pin Dynamics Each input to the LT1116 is buffered with a fast PNP The internal latch uses local regenerative feedback to follower—input bias current therefore does not vary shorten set-up and hold times. Driving the latch pin high significantly throughout the common mode range. When retains the output state. The latch pin floats to a high either input exceeds the positive common mode limit, the state when disconnected, so it must be driven low for bias current drops to zero. Inputs that fall more than one flow-through operation. The set-up time required to diode and drop below V– will forward bias the substrate guarantee detecting a given transition of the inputs is 2ns. or clamp diode, causing large input current to flow. The inputs must also remain stable for a 2ns hold time Single ended input resistance is about 5MΩ, and re- after latch is asserted. New data will appear at the output mains roughly constant over the input common mode approximately 10ns to 12ns after the latch goes low. The range. The common mode resistance is about 2.5MΩ latch pin has no built-in hysteresis, and is designed to be with zero differential input voltage, and does not change driven from TTL or CMOS logic gates. signifi cantly with the absolute value of differential input. Additional Information Effective input capacitance, typically 5pF, is determined Linear Technology’s Application Note 13 provides an by measuring the resulting change in propagation delay extensive discussion of design techniques for high speed for a 1kΩ change in source resistance. comparators. Single Supply Crystal Oscillator 10MHz to 15MHz 10 TO 15MHz 1kΩ AT CUT 5V 5V Q + LT1116 1kΩ – OUTPUT Q 24pF 2kΩ LT1116 • AI02 Figure 2. This Single Supply Crystal Oscillator Utilizes CrystalsFrom 10MHz To 15MHz Without Component Changes 1116fc For more information www.linear.com/LT1116 7