Datasheet AD654 (Analog Devices) - 5

AD654 CIRCUIT OPERATION V/F CONNECTIONS FOR NEGATIVE INPUT VOLTAGE
The AD654’s block diagram appears in Figure 1. A versatile
OR CURRENT
operational amplifier serves as the input stage; its purpose is to The AD654 can accommodate a wide range of negative input convert and scale the input voltage signal to a drive current in the voltages with proper selection of the scaling resistor, as indicated NPN follower. Optimum performance is achieved when, at the in Figure 2. This connection, unlike the buffered positive con- full-scale input voltage, a 1 mA drive current is delivered to the nection, is not high impedance because the signal source must current-to-frequency converter (an astable multivibrator). The supply the 1 mA FS drive current. However, large negative volt- drive current provides both the bias levels and the charging current ages beyond the supply can be handled easily by modifying the to the externally connected timing capacitor. This “adaptive” bias scaling resistors appropriately. If the input is a true current source, scheme allows the oscillator to provide low nonlinearity over R1 and R2 are not used. Again, diode CR1 prevents latch-up by the entire current input range of 100 nA to 2 mA. The square insuring Logic Common does not drop more than 500 mV below wave oscillator output goes to the output driver which provides –VS. The clamp diode (MBD101) protects the AD654 input a floating base drive to the NPN power transistor. This floating from “below –VS” inputs. drive allows the logic interface to be referenced to a level other
+V
than –V
S
S.
(+5V TO –V +V S +30) CT LOGIC +VS R (+5V TO –V +V PU S +30) CT LOGIC OPTIONAL FOUT R R OSC/ PU COMP DRIVER OPTIONAL FOUT VIN F R OSC/ OUT = COMP (10V) (R1 + R2) C V DRIVER R1 R2 AD654 T IN V V IN IN FOUT = AD654 (10V) (R1 + R2) CT CLAMP DIODE R1 CR1 –VS R2 (0V TO –15V) CR1 –V
Figure 2. V-F Connections for Negative Input Voltages or
S (0V TO –15V)
Current Figure 1. Standard V-F Connection for Positive Input Voltages
OFFSET CALIBRATION
In theory, two adjustments calibrate a V/F: scale and offset. In
V/F CONNECTION FOR POSITIVE INPUT VOLTAGES
practice, most applications find the AD654’s 1 mV max voltage In the connection scheme of Figure 1, the input amplifier presents offset sufficiently low to forgo offset calibration. However, the a very high (250 MΩ) impedance to the input voltage, which input amplifier’s 30 nA (typ) bias currents will generate an offset is converted into the proper drive current by the scaling resistors due to the difference in dc sound resistance between the input at Pin 3. Resistors R1 and R2 are selected to provide a 1 mA terminals. This offset can be substantial for large values of RT = full-scale current with enough trim range to accommodate the R1 + R2 and will vary as the bias currents drift over temperature. AD654’s 10% FS error and the components’ tolerances. Full- Therefore, to maintain the AD654’s low offset, the application may scale currents other than 1 mA can be chosen, but linearity will require balancing the dc source resistances at the inputs (Pins be reduced; 2 mA is the maximum allowable drive. The AD654’s 3 and 4). positive input voltage range spans from –VS (ground in sink supply For positive inputs, this is accomplished by adding a compensation operation) to four volts below the positive supply. Power sup- resistor nominally equal to R ply rejection degrades as the input exceeds (+V T in series with the input as shown S – 3.75 V) and at in Figure 3a. This limits the offset to the product of the 30 nA (+VS – 3.5 V) the output frequency goes to zero. bias current and the mismatch between the source resistance RT As indicated by the scaling relationship in Figure 1, a 0.01 µF and RCOMP. A second, smaller offset arises from the inputs’ 5 nA timing capacitor will give a 10 kHz full-scale frequency, and offset current flowing through the source resistance RT or RCOMP. 0.001 µF will give 100 kHz with a 1 mA drive current. Good V/F For negative input voltage and current connections, the compensa- linearity requires the use of a capacitor with low dielectric tion resistor is added at Pin 4 as shown in Figure 3b in lieu of absorption (DA), while the most stable operation over tempera- grounding the pin directly. For both positive and negative inputs, ture calls for a component having a small tempco. Polystyrene, the use of RCOMP may lead to noise coupling at Pin 4 and should polypropylene, or Teflon* capacitors are preferred for tempco and therefore be bypassed for lowest noise operation. dielectric absorption; other types will degrade linearity. The capacitor should be wired very close to the AD654. In Figure 1,
(OPTIONAL) C
Schottky diode CR1 (MBD101) prevents logic common from
AD654
dropping more than 500 mV below –VS. This diode is not
VIN
required if –V
R
S is equal to logic common.
COMP R1 R2
Figure 3a. Bias Current Compensation—Positive Inputs *Teflon is a trademark of E.I. Du Pont de Nemours & Co. –4– REV. C