AD8250. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. 1400. 500. 1200. 400. 1000. 300. U 800. UNI F. E 600. BE 200. M U N. NUM. 100. 200. –120. –90. –60
AD8250Data SheetTYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, +VS = +15 V, −VS = −15 V, RL = 10 kΩ, unless otherwise noted. 140050012004001000SSITTN300U 800UNI FOFORRE 600BBE 200M U NNUM40010020000 06 09 –120–90–60–300306090120 0 –30–20–100102030 0 8- 8- 28 CMRR (µV/V)INPUT OFFSET CURRENT (nA) 28 06 06 Figure 6. Typical Distribution of CMRR, G = 1 Figure 9. Typical Distribution of Input Offset Current 350908030070250)Sz60TH /200VUNI50FI (nOG = 1RRT15040EBEISG = 230NUMNO100G = 520G = 105010 10 0 8- 28 06 00 1101001k10k100k–200–150–100–50050100150200 07 0 8- FREQUENCY (Hz)OFFSET VOLTAGE RTI (µV) 28 06 Figure 7. Typical Distribution of Offset Voltage, VOSI Figure 10. Voltage Spectral Density Noise vs. Frequency 600500S IT 400N UOF 300R E B M U N 200100 1 2µV/DIV1s/DIV -01 0 88 –30–20–100102030 08 0 62 8- 0 INPUT BIAS CURRENT (nA) 28 06 Figure 8. Typical Distribution of Input Bias Current Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 1 Rev. C | Page 8 of 24 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Diagram Absolute Maximum Ratings Maximum Power Dissipation ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Gain Selection Transparent Gain Mode Latched Gain Mode Timing for Latched Gain Mode Power Supply Regulation and Bypassing Input Bias Current Return Path Input Protection Reference Terminal Common-Mode Input Voltage Range Layout Grounding Coupling Noise Common-Mode Rejection RF Interference Driving an ADC Applications Differential Output Setting Gains with a Microcontroller Data Acquisition Outline Dimensions Ordering Guide