Datasheet ESP8266EX (Espressif) - 10

FabricanteEspressif
DescripciónWith the complete and self-contained Wi-Fi networking capabilities, ESP8266EX can perform either as a standalone application or as the slave to a host MCU
Páginas / Página27 / 10 — 2. Pin. Definitions. !. Pin. Name. Type. Function. 9. MTMS. I/O. GPIO14;. …
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2. Pin. Definitions. !. Pin. Name. Type. Function. 9. MTMS. I/O. GPIO14;. HSPI_CLK. 10. MTDI. I/O. GPIO12;. HSPI_MISO. 11. VDDPST. P. Digital/IO. Power. Supply. (1.8. V. ~

2 Pin Definitions ! Pin Name Type Function 9 MTMS I/O GPIO14; HSPI_CLK 10 MTDI I/O GPIO12; HSPI_MISO 11 VDDPST P Digital/IO Power Supply (1.8 V ~

Versión de texto del documento

2. Pin Definitions ! Pin Name Type Function 9 MTMS I/O GPIO14; HSPI_CLK 10 MTDI I/O GPIO12; HSPI_MISO 11 VDDPST P Digital/IO Power Supply (1.8 V ~ 3.3 V) 12 MTCK I/O GPIO13; HSPI_MOSI; UART0_CTS 13 MTDO I/O GPIO15; HSPI_CS; UART0_RTS 14 GPIO2 I/O UART Tx during flash programming; GPIO2 15 GPIO0 I/O GPIO0; SPI_CS2 16 GPIO4 I/O GPIO4 17 VDDPST P Digital/IO Power Supply (1.8 V ~ 3.3 V) 18 SDIO_DATA_2 I/O Connect to SD_D2 (Series R: 200Ω); SPIHD; HSPIHD; GPIO9 19 SDIO_DATA_3 I/O Connect to SD_D3 (Series R: 200Ω); SPIWP; HSPIWP; GPIO10 20 SDIO_CMD I/O Connect to SD_CMD (Series R: 200Ω); SPI_CS0; GPIO11 21 SDIO_CLK I/O Connect to SD_CLK (Series R: 200Ω); SPI_CLK; GPIO6 22 SDIO_DATA_0 I/O Connect to SD_D0 (Series R: 200Ω); SPI_MSIO; GPIO7 23 SDIO_DATA_1 I/O Connect to SD_D1 (Series R: 200Ω); SPI_MOSI; GPIO8 24 GPIO5 I/O GPIO5 25 U0RXD I/O UART Rx during flash programming; GPIO3 26 U0TXD I/O UART Tx during flash progamming; GPIO1; SPI_CS1 Connect to crystal oscillator output, can be used to provide BT 27 XTAL_OUT I/O clock input 28 XTAL_IN I/O Connect to crystal oscillator input 29 VDDD P Analog Power 3.0 V ~ 3.6 V 30 VDDA P Analog Power 3.0 V ~ 3.6 V Serial connection with a 12 kΩ resistor and connect to the 31 RES12K I ground 32 EXT_RSTB I External reset signal (Low voltage level: Active) Note GPIO2, GPIO0, and MTDO are configurable on PCB as the 3-bit strapping register that determines the booting mode and the SDIO timing mode. Espressif ! / 6 !23 2016.04