Datasheet Microchip PL500-17SI — Ficha de datos

PL500-17
Low Phase Noise VCXO (17MHz to 36MHz)
FEATURES
п‚ п‚ DESCRIPTION XIN 1 VDD* 2 VCON 3 GND 4 8 XOUT 7 OE^ 6 VDD* 5 CLK SOP-8L XOUT 1 GND 2 CLK 3 PL500-17 VCXO output for the 17MHz to 36MHz range
Low phase noise (-130dBc @ 10kHz offset at
35.328MHz)
LVCMOS output with OE tri-state control
17 to 36MHz fundamental crystal input
Integrated high linearity variable capacitors
8mA drive capability at TTL output
В±150 ppm pull range, max 5% (typ.) linearity
Low jitter (RMS): 2.5ps period jitter
2.5 to 3.3V operation
Available in 8-Pin SOP, 6-pin SOT23 GREEN/
RoHS compliant packages, or Die PL500-17 п‚ п‚ п‚ п‚ п‚ п‚ п‚ п‚ PIN CONFIGURATION 6 XIN 5 VDD 4 VCON SOT23-6L The PL500-17 is a low cost, high performance and
low phase noise VCXO for the 17 to 36MHz range,
providing less than -130dBc at 10kHz offset at
35.328MHz. The very low jitter (2.5 ps RMS period
jitter) makes this chip ideal for applications requiring
voltage controlled frequency sources. Input crystal
can range from 17 to 36MHz (fundamental resonant
mode). ^: Denotes internal Pull-up
*: Only one VDD pin needs to be connected BLOCK DIAGRAM XIN Xtal …