Datasheet Microchip PIC16F15356T-I/ML — Ficha de datos

PIC16(L)F15356/75/76/85/86
Full-Featured 28/40/44/48-Pin Microcontrollers
Description
PIC16(L)F15356/75/76/85/86 microcontrollers feature Analog, Core Independent Peripherals and Communication
Peripherals, combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power
applications.
The devices feature multiple PWMs, multiple communication, temperature sensor, and memory features like Memory
Access Partition (MAP) to support customers in data protection and bootloader applications, and Device Information
Area (DIA) which stores factory calibration values to help improve temperature sensor accuracy. Core Features Power-Saving Functionality • C Compiler Optimized RISC Architecture
• Operating Speed:
-DC – 32 MHz clock input
-125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Timers:
-8-bit Timer2 with Hardware Limit Timer (HLT)
-16-bit Timer0/1
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRTE)
• Brown-out Reset (BOR)
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT):
-Variable prescaler selection …

PIC16(L)F15356/75/76/85/86
Full-Featured 28/40/44/48-Pin Microcontrollers
Description
PIC16(L)F15356/75/76/85/86 microcontrollers feature Analog, Core Independent Peripherals and Communication
Peripherals, combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power
applications.
The devices feature multiple PWMs, multiple communication, temperature sensor, and memory features like Memory
Access Partition (MAP) to support customers in data protection and bootloader applications, and Device Information
Area (DIA) which stores factory calibration values to help improve temperature sensor accuracy. Core Features Power-Saving Functionality C Compiler Optimized RISC Architecture Only 48 Instructions Operating Speed:
-DC – 32 MHz clock input
-125 ns minimum instruction cycle Interrupt Capability 16-Level Deep Hardware Stack Timers:
-8-bit Timer2 with Hardware Limit Timer (HLT)
-16-bit Timer0/1 Low-Current Power-on Reset (POR) Configurable Power-up Timer (PWRTE) Brown-out Reset (BOR) Low-Power BOR (LPBOR) Option Windowed Watchdog Timer (WWDT):
-Variable prescaler selection
-Variable window size selection
-All sources configurable in hardware or
software Programmable Code Protection DOZE mode: Ability to Run the CPU Core Slower
than the System Clock IDLE mode: Ability to halt CPU Core while Internal
Peripherals Continue Operating SLEEP mode: Lowest Power Consumption Peripheral Module Disable (PMD):
-Ability to disable hardware module to
minimize active power consumption of
unused peripherals Memory Up to 28 KB Flash Program Memory
Up to 2 KB Data SRAM …