Datasheet Linear Technology LTC2209 — Ficha de datos

Fabricante	Linear Technology
Serie	LTC2209

ADC de 16 bits, 160Msps

Hojas de datos

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PDF, 612 Kb, Idioma: en, Archivo subido: agosto 19, 2017, Páginas: 32
16-Bit, 160Msps ADC

Extracto del documento

Precios

Embalaje

	LTC2209CUP#PBF	LTC2209CUP#TRPBF	LTC2209IUP#PBF	LTC2209IUP#TRPBF
N	1	2	3	4
Package	9x9 QFN-64 Dibujo del esquema del paquete	9x9 QFN-64 Dibujo del esquema del paquete	9x9 QFN-64 Dibujo del esquema del paquete	9x9 QFN-64 Dibujo del esquema del paquete
Package Code	UP	UP	UP	UP
Package Index	05-08-1705	05-08-1705	05-08-1705	05-08-1705
Pin Count	64	64	64	64

Paramétricos

Parameters / Models	LTC2209CUP#PBF	LTC2209CUP#TRPBF	LTC2209IUP#PBF	LTC2209IUP#TRPBF
ADC INL, LSB	1.5	1.5	1.5	1.5
ADCs	1	1	1	1
Architecture	Pipeline	Pipeline	Pipeline	Pipeline
Bipolar/Unipolar Input	Bipolar	Bipolar	Bipolar	Bipolar
Bits, bits	16	16	16	16
Number of Channels	1	1	1	1
DNL, LSB	0.3	0.3	0.3	0.3
Demo Boards	DC1281A-A,DC1281A-B,DC1282A-A	DC1281A-A,DC1281A-B,DC1282A-A	DC1281A-A,DC1281A-B,DC1282A-A	DC1281A-A,DC1281A-B,DC1282A-A
Export Control	yes	yes	yes	yes
Features	Internal Dither, PGA, Data Output Randomizer, Clock Duty Cycle Stabilizer	Internal Dither, PGA, Data Output Randomizer, Clock Duty Cycle Stabilizer	Internal Dither, PGA, Data Output Randomizer, Clock Duty Cycle Stabilizer	Internal Dither, PGA, Data Output Randomizer, Clock Duty Cycle Stabilizer
I/O	Parallel CMOS, Parallel LVDS	Parallel CMOS, Parallel LVDS	Parallel CMOS, Parallel LVDS	Parallel CMOS, Parallel LVDS
Input Drive	Differential	Differential	Differential	Differential
Input Span	2.25Vpp or 1.5Vpp	2.25Vpp or 1.5Vpp	2.25Vpp or 1.5Vpp	2.25Vpp or 1.5Vpp
Internal Reference	yes	yes	yes	yes
Latency	7	7	7	7
Operating Temperature Range, °C	0 to 70	0 to 70	-40 to 85	-40 to 85
Power, mW	1450	1450	1450	1450
SFDR, dB	100	100	100	100
SINAD, dB	77.1	77.1	77.1	77.1
SNR, dB	77.1	77.1	77.1	77.1
Simultaneous	no	no	no	no
Speed, ksps	160000	160000	160000	160000
Supply Voltage Range	3.3V	3.3V	3.3V	3.3V

Plan ecológico

	LTC2209CUP#PBF	LTC2209CUP#TRPBF	LTC2209IUP#PBF	LTC2209IUP#TRPBF
RoHS	Obediente	Obediente	Obediente	Obediente

Notas de Diseño

Descargar
Understanding the Effect of Clock Jitter on High Speed ADCs &mdash DN1013
PDF, 115 Kb, Archivo publicado: agosto 28, 2007
Extracto del documento
advertisement Understanding the Effect of Clock Jitter on High Speed ADCs
Design Note 1013
Derek Redmayne (LTC Applications Engineer), Eric Trelewicz (LTC Applications
Manager) and Alison Smith (High Speed ADC Product Marketing Engineer)
Digitizing high speed signals to a high resolution requires
careful selection of a clock that will not compromise the
sampling performance of the Analog to Digital Converter
(ADC). In this article we hope to give the reader a better understanding of clock jitter and how it affects the
performance of the high speed ADC.
As an example we will highlight the latest high performance ADC from Linear Technology, the 16-bit, 160Msps
LTC2209. This ADC exhibits a signal to noise ratio (SNR)
of 77.4dB, with 100dB SFDR throughout much of the
baseband region. Like most high speed ADCs on the
market today, the LTC2209 uses a sample-and-hold (S&H)
circuit that essentially takes a snapshot of the ADC input
at an instant in time. When the S&H switch is closed,
the network at the input of the ADC is connected to the
sample capacitor. At the instant the switch is opened
one half clock cycle later, the voltage on the capacitor
is recorded and held. Variation in the time at which the
switch is opened is known as aperture uncertainty, or jitter, and will result in an error voltage that is proportional
to the magnitude of the jitter and the input signal slew
rate. In other words, the greater the input frequency and …

Linea modelo

Serie: LTC2209 (4)

LTC2209CUP#PBF LTC2209CUP#TRPBF LTC2209IUP#PBF LTC2209IUP#TRPBF

Clasificación del fabricante

Data Conversion > Analog-to-Digital Converters (ADC) > High Speed ADCs (Fs >=10Msps)