Datasheet Atmel ATmega103-6AI — Ficha de datos

Features
• Utilizes the AVR® RISC Architecture
• AVR - High-performance and Low-power RISC Architecture • • • •
• •
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• - 121 Powerful Instructions - Most Single Clock Cycle Execution
- 32 x 8 General Purpose Working Registers + Peripheral Control Registers
- Up to 6 MIPS Throughput at 6 MHz
Data and Nonvolatile Program Memory
- 128K Bytes of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
- 4K Bytes Internal SRAM
- 4K Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
- Programming Lock for Flash Program and EEPROM Data Security
- SPI Interface for In-System Programming
Peripheral Features
- On-chip Analog Comparator
- Programmable Watchdog Timer with On-chip Oscillator
- Programmable Serial UART
- Master/Slave SPI Serial Interface
- Real-time Counter (RTC) with Separate Oscillator
- Two 8-bit Timer/Counters with Separate Prescaler and PWM …