Datasheet Texas Instruments TLV1578 — Ficha de datos

FabricanteTexas Instruments
SerieTLV1578
Datasheet Texas Instruments TLV1578

8-ch. 10 bits 1.25 MSPS ADC 8 canales, DSP / SPI, configurable por hardware, baja potencia

Hojas de datos

2.7 V to 5.5 V, 1-/-8 Channel 10-Bit Parallel Analog-to-Digital Converters datasheet
PDF, 627 Kb, Revisión: D, Archivo publicado: jul 11, 2000
Extracto del documento

Precios

Estado

TLV1578CDATLV1578CDAG4TLV1578CDARTLV1578CDARG4TLV1578IDATLV1578IDAG4
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNoNo

Embalaje

TLV1578CDATLV1578CDAG4TLV1578CDARTLV1578CDARG4TLV1578IDATLV1578IDAG4
N123456
Pin323232323232
Package TypeDADADADADADA
Industry STD TermTSSOPTSSOPTSSOPTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY4646200020004646
CarrierTUBETUBELARGE T&RLARGE T&RTUBETUBE
Device MarkingTLV1578TLV1578TLV1578TLV1578TLV1578ITLV1578I
Width (mm)6.26.26.26.26.26.2
Length (mm)111111111111
Thickness (mm)1.151.151.151.151.151.15
Pitch (mm).65.65.65.65.65.65
Max Height (mm)1.21.21.21.21.21.2
Mechanical DataDescargarDescargarDescargarDescargarDescargarDescargar

Paramétricos

Parameters / ModelsTLV1578CDA
TLV1578CDA
TLV1578CDAG4
TLV1578CDAG4
TLV1578CDAR
TLV1578CDAR
TLV1578CDARG4
TLV1578CDARG4
TLV1578IDA
TLV1578IDA
TLV1578IDAG4
TLV1578IDAG4
# Input Channels888888
Analog Voltage AVDD(Max), V5.55.55.55.55.55.5
Analog Voltage AVDD(Min), V2.72.72.72.72.72.7
ArchitectureSARSARSARSARSARSAR
Digital Supply(Max), V5.55.55.55.55.55.5
Digital Supply(Min), V2.72.72.72.72.72.7
INL(Max), +/-LSB111111
Input Range(Max), V5.55.55.55.55.55.5
Input TypeSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-Ended
Integrated FeaturesOscillatorOscillatorOscillatorOscillatorOscillatorOscillator
InterfaceParallelParallelParallelParallelParallelParallel
Multi-Channel ConfigurationMultiplexedMultiplexedMultiplexedMultiplexedMultiplexedMultiplexed
Operating Temperature Range, C-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70
Package GroupTSSOPTSSOPTSSOPTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG32TSSOP: 89 mm2: 8.1 x 11(TSSOP)32TSSOP: 89 mm2: 8.1 x 11(TSSOP)32TSSOP: 89 mm2: 8.1 x 11(TSSOP)32TSSOP: 89 mm2: 8.1 x 11(TSSOP)32TSSOP: 89 mm2: 8.1 x 11(TSSOP)32TSSOP: 89 mm2: 8.1 x 11(TSSOP)
Power Consumption(Typ), mW121212121212
RatingCatalogCatalogCatalogCatalogCatalogCatalog
Reference ModeExtExtExtExtExtExt
Resolution, Bits101010101010
SINAD, dB606060606060
SNR, dB606060606060
Sample Rate (max), SPS1.25MSPS1.25MSPS1.25MSPS1.25MSPS1.25MSPS1.25MSPS
Sample Rate(Max), MSPS1.251.251.251.251.251.25
THD(Typ), dB-60-60-60-60-60-60

Plan ecológico

TLV1578CDATLV1578CDAG4TLV1578CDARTLV1578CDARG4TLV1578IDATLV1578IDAG4
RoHSObedienteObedienteObedienteObedienteObedienteObediente

Notas de aplicación

  • Interfacing the TLV1571/78 Analog-to-Digital Converter to the TMS320C542 DSP
    PDF, 192 Kb, Archivo publicado: oct 7, 1999
    This application report presents a hardware solution for interfacing the TLV1571/TLV1578 10-bit, 1.25 MSPS low-power analog-to-digital converter (ADC) to the 16-bit fixed-point TMS320C542 digital signal processor (DSP). The report describes the interface hardware and C-callable software routines, which support communication between ADC and DSP.
  • Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, Revisión: A, Archivo publicado: nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
  • Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, Archivo publicado: marzo 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to

Linea modelo

Clasificación del fabricante

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> Precision ADCs (<=10MSPS)