Datasheet Texas Instruments TLV1572 — Ficha de datos

FabricanteTexas Instruments
SerieTLV1572
Datasheet Texas Instruments TLV1572

10 bits, 1.25 MSPS ADC Single Ch., DSP / (Q) SPI IF, S&H, muy baja potencia, Auto PowerDown

Hojas de datos

2.8V to 5.5V 10-Bit 1.25 MSPS Serial A-D Converter With Auto-Power-Down datasheet
PDF, 732 Kb, Revisión: A, Archivo publicado: sept 4, 1998
Extracto del documento

Precios

Estado

TLV1572CDTLV1572CDG4TLV1572CDRTLV1572CDRG4TLV1572IDTLV1572IDG4TLV1572IDRTLV1572IDRG4
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNoNo

Embalaje

TLV1572CDTLV1572CDG4TLV1572CDRTLV1572CDRG4TLV1572IDTLV1572IDG4TLV1572IDRTLV1572IDRG4
N12345678
Pin88888888
Package TypeDDDDDDDD
Industry STD TermSOICSOICSOICSOICSOICSOICSOICSOIC
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY757525002500757525002500
CarrierTUBETUBELARGE T&RLARGE T&RTUBETUBELARGE T&RLARGE T&R
Device MarkingV1572CV1572CV1572CV1572CV1572IV1572IV1572IV1572I
Width (mm)3.913.913.913.913.913.913.913.91
Length (mm)4.94.94.94.94.94.94.94.9
Thickness (mm)1.581.581.581.581.581.581.581.58
Pitch (mm)1.271.271.271.271.271.271.271.27
Max Height (mm)1.751.751.751.751.751.751.751.75
Mechanical DataDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargar

Paramétricos

Parameters / ModelsTLV1572CD
TLV1572CD
TLV1572CDG4
TLV1572CDG4
TLV1572CDR
TLV1572CDR
TLV1572CDRG4
TLV1572CDRG4
TLV1572ID
TLV1572ID
TLV1572IDG4
TLV1572IDG4
TLV1572IDR
TLV1572IDR
TLV1572IDRG4
TLV1572IDRG4
# Input Channels11111111
Analog Voltage AVDD(Max), V5.55.55.55.55.55.55.55.5
Analog Voltage AVDD(Min), V2.72.72.72.72.72.72.72.7
ArchitectureSARSARSARSARSARSARSARSAR
Digital Supply(Max), V5.55.55.55.55.55.55.55.5
Digital Supply(Min), V2.72.72.72.72.72.72.72.7
INL(Max), +/-LSB11111111
Input Range(Max), V5.55.55.55.55.55.55.55.5
Input TypeSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-Ended
Integrated FeaturesN/AN/AN/AN/AN/AN/AN/AN/A
InterfaceSPISPISPISPISPISPISPISPI
Multi-Channel ConfigurationN/AN/AN/AN/AN/AN/AN/AN/A
Operating Temperature Range, C-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70
Package GroupSOICSOICSOICSOICSOICSOICSOICSOIC
Package Size: mm2:W x L, PKG8SOIC: 29 mm2: 6 x 4.9(SOIC)8SOIC: 29 mm2: 6 x 4.9(SOIC)8SOIC: 29 mm2: 6 x 4.9(SOIC)8SOIC: 29 mm2: 6 x 4.9(SOIC)8SOIC: 29 mm2: 6 x 4.9(SOIC)8SOIC: 29 mm2: 6 x 4.9(SOIC)8SOIC: 29 mm2: 6 x 4.9(SOIC)8SOIC: 29 mm2: 6 x 4.9(SOIC)
Power Consumption(Typ), mW88888888
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Reference ModeExtExtExtExtExtExtExtExt
Resolution, Bits1010101010101010
SINAD, dB6060606060606060
SNR, dB6262626262626262
Sample Rate (max), SPS1.25MSPS1.25MSPS1.25MSPS1.25MSPS1.25MSPS1.25MSPS1.25MSPS1.25MSPS
Sample Rate(Max), MSPS1.251.251.251.251.251.251.251.25
THD(Typ), dB-60-60-60-60-60-60-60-60

Plan ecológico

TLV1572CDTLV1572CDG4TLV1572CDRTLV1572CDRG4TLV1572IDTLV1572IDG4TLV1572IDRTLV1572IDRG4
RoHSObedienteObedienteObedienteObedienteObedienteObedienteObedienteObediente

Notas de aplicación

  • Low-power data acquisition sub-system using the TI TLV1572
    PDF, 230 Kb, Archivo publicado: marzo 11, 2005
  • Interfacing the TLV1572 Analog-to-Digital Converter to the TMS320C203 DSP (Rev. B)
    PDF, 135 Kb, Revisión: B, Archivo publicado: mayo 11, 1999
    This application report presents a hardware solution for interfacing the TLV1572 10-bit, 1.25 MSPS (Mega Samples Per Second), successive low-power analog-to-digital converter (ADC) to the TMS320C203 16-bit fixed-point digital signal processor (DSP). In addition, a C-callable interface program is shown which supports the data transfer between ADC and DSP.
  • Low-Power Signal Conditioning For A Pressure Sensor (Rev. A)
    PDF, 469 Kb, Revisión: A, Archivo publicado: mayo 18, 2015
  • Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, Revisión: A, Archivo publicado: nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
  • Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, Archivo publicado: marzo 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to

Linea modelo

Clasificación del fabricante

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> Precision ADCs (<=10MSPS)