Datasheet Texas Instruments TLC5540 — Ficha de datos

FabricanteTexas Instruments
SerieTLC5540
Datasheet Texas Instruments TLC5540

Convertidor analógico a digital (ADC) de 8 bits y 40 MSPS

Hojas de datos

TLC5540: 8-Bit High-Speed Analog-to-Digital Converter (Rev. D)
PDF, 872 Kb, Revisión: D, Archivo publicado: abr 19, 2004
TLC5540: 8-Bit High-Speed Analog-to-Digital Converter datasheet
PDF, 867 Kb, Revisión: D, Archivo publicado: abr 19, 2004
Extracto del documento

Precios

Estado

TLC5540CNSLETLC5540CNSRTLC5540CPWTLC5540INSLETLC5540INSRTLC5540INSRG4TLC5540IPWTLC5540IPWR
Estado del ciclo de vidaObsoleto (El fabricante ha interrumpido la producción del dispositivo)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Obsoleto (El fabricante ha interrumpido la producción del dispositivo)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNoNoNoNoNo

Embalaje

TLC5540CNSLETLC5540CNSRTLC5540CPWTLC5540INSLETLC5540INSRTLC5540INSRG4TLC5540IPWTLC5540IPWR
N12345678
Pin2424242424242424
Package TypeNSNSPWNSNSNSPWPW
Industry STD TermSOPSOPTSSOPSOPSOPSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Width (mm)5.35.34.45.35.35.34.44.4
Length (mm)15157.81515157.87.8
Thickness (mm)1.951.9511.951.951.9511
Pitch (mm)1.271.27.651.271.271.27.65.65
Max Height (mm)221.22221.21.2
Mechanical DataDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargar
Package QTY20006020002000602000
CarrierLARGE T&RTUBELARGE T&RLARGE T&RTUBELARGE T&R
Device MarkingTLC5540P5540TLC5540ITLC5540IY5540Y5540

Paramétricos

Parameters / ModelsTLC5540CNSLE
TLC5540CNSLE
TLC5540CNSR
TLC5540CNSR
TLC5540CPW
TLC5540CPW
TLC5540INSLE
TLC5540INSLE
TLC5540INSR
TLC5540INSR
TLC5540INSRG4
TLC5540INSRG4
TLC5540IPW
TLC5540IPW
TLC5540IPWR
TLC5540IPWR
# Input Channels11111111
Analog Input BW, MHz7575757575
Analog Input BW(MHz)757575
Approx. Price (US$)2.64 | 1ku2.64 | 1ku2.64 | 1ku
ArchitectureFlashFlashFlashFlashFlashFlashFlashFlash
DNL(Max)(+/-LSB)111
DNL(Typ), +/-LSB0.20.20.20.20.2
ENOB, Bits6.86.86.86.86.8
ENOB(Bits)6.86.86.8
INL(Max)(+/-LSB)111
INL(Typ), +/-LSB0.60.60.60.60.6
Input BufferNoNoNoNoNoNoNo
Input Range, Vp-p+2V22+2V2+2V22
InterfaceParallel CMOSParallel CMOSParallel CMOSParallel CMOSParallel CMOSParallel CMOSParallel CMOSParallel CMOS
Operating Temperature Range, C-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70-40 to 85,0 to 70
Operating Temperature Range(C)-40 to 85
0 to 70
-40 to 85
0 to 70
-40 to 85
0 to 70
Package GroupSOSOTSSOPSOSOSOTSSOPTSSOP
Package Size(mm2=WxL)24TSSOP: 50 mm2: 6.4 x 7.8
Package Size: mm2:W x L, PKG24SO: 117 mm2: 7.8 x 15(SO)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)24SO: 117 mm2: 7.8 x 15(SO)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)
Package Size: mm2:W x L (PKG)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)
Power Consumption(Typ), mW8585858585
Power Consumption(Typ)(mW)858585
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Reference ModeExtExtExtExtExtExtExtExt
Resolution, Bits88888
Resolution(Bits)888
SFDR, dB4242424242
SFDR(dB)424242
SINAD, dB43.343.343.343.343.3
SNR, dB4444444444
SNR(dB)444444
Sample Rate (max)(SPS)40MSPS
Sample Rate(Max), MSPS4040404040
Sample Rate(Max)(MSPS)4040

Plan ecológico

TLC5540CNSLETLC5540CNSRTLC5540CPWTLC5540INSLETLC5540INSRTLC5540INSRG4TLC5540IPWTLC5540IPWR
RoHSDesobedienteObedienteObedienteDesobedienteObedienteObedienteObedienteObediente
Pb gratisNoNo

Notas de aplicación

  • Interfacing A/D Converters TLC5540/10 to the DSKplus DSP Starter Kit TMS320C54x
    PDF, 206 Kb, Archivo publicado: abr 1, 1997
    This Application Note describes the construction of a test circuit using the A/D converters TLC5540 and TLC5510, and alternative ways of interfacing these converters to the DSKplus DSP starter kit TMS
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, Archivo publicado: sept 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527, which is capable of sampling up to 210 MSPS. To realize the full potential of thes
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, Archivo publicado: abr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the refe
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed, high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483, which is capable of
  • Interfacing the TLC5540 Analog To Digital Converter to the TMS320C203-80 DSP
    PDF, 763 Kb, Archivo publicado: marzo 1, 1998
    CMOS analog-to-digital converters (ADCs) are used as basic building blocks in many types of data acquisition systems.This application report describes the interface between the high-speed Texas Instruments (TI?TLC5540 8-bit parallel-output ADC and the TI TMS320C203-80 digital signal processor (DSP). The 8-bit resolution ADC can operate at a rate of up to 40MSa/s (megasamples per second). On-ch
  • Interfacing A/D Converters TLC5540/10 to the DSKplus DSP Starter Kit TMS320C54x
    PDF, 206 Kb, Archivo publicado: abr 1, 1997
    This Application Note describes the construction of a test circuit using the A/D converters TLC5540 and TLC5510, and alternative ways of interfacing these converters to the DSKplus DSP starter kit TMS320C54x. Details are given of the test circuit of the TLC5540/10 and of the interface, and the programming of the digital signal processor TMS320C54x is also described.
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, Archivo publicado: sept 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, Archivo publicado: abr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revisión: A, Archivo publicado: sept 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, Archivo publicado: jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

Linea modelo

Clasificación del fabricante

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)