Datasheet Texas Instruments TLC2552 — Ficha de datos

Fabricante	Texas Instruments
Serie	TLC2552

12 bits, 400 kSPS ADC, salida serie, compatible con TMS320 (hasta 10MHz), doble canal. Barrido automático

Hojas de datos

PDF, 1.1 Mb, Revisión: D, Archivo publicado: oct 17, 2002

Extracto del documento

	TLC2552CDGK	TLC2552CDGKG4	TLC2552ID	TLC2552IDG4	TLC2552IDGK	TLC2552IDGKG4
Estado del ciclo de vida	Activo (Recomendado para nuevos diseños)	Activo (Recomendado para nuevos diseños)	Activo (Recomendado para nuevos diseños)	Activo (Recomendado para nuevos diseños)	Activo (Recomendado para nuevos diseños)	Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricante	No	No	No	No	No	No

	TLC2552CDGK	TLC2552CDGKG4	TLC2552ID	TLC2552IDG4	TLC2552IDGK	TLC2552IDGKG4
N	1	2	3	4	5	6
Pin	8	8	8	8	8	8
Package Type	DGK	DGK	D	D	DGK	DGK
Industry STD Term	VSSOP	VSSOP	SOIC	SOIC	VSSOP	VSSOP
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G
Package QTY	80	80	75	75	80	80
Carrier	TUBE	TUBE	TUBE	TUBE	TUBE	TUBE
Device Marking	AHH	AHH	2552I	2552I	AHI	AHI
Width (mm)	3	3	3.91	3.91	3	3
Length (mm)	3	3	4.9	4.9	3	3
Thickness (mm)	.97	.97	1.58	1.58	.97	.97
Pitch (mm)	.65	.65	1.27	1.27	.65	.65
Max Height (mm)	1.07	1.07	1.75	1.75	1.07	1.07
Mechanical Data	Descargar	Descargar	Descargar	Descargar	Descargar	Descargar

Parameters / Models	TLC2552CDGK	TLC2552CDGKG4	TLC2552ID	TLC2552IDG4	TLC2552IDGK	TLC2552IDGKG4
# Input Channels	2	2	2	2	2	2
Analog Voltage AVDD(Max), V	5.5	5.5	5.5	5.5	5.5	5.5
Analog Voltage AVDD(Min), V	4.5	4.5	4.5	4.5	4.5	4.5
Architecture	SAR	SAR	SAR	SAR	SAR	SAR
Digital Supply(Max), V	5.5	5.5	5.5	5.5	5.5	5.5
Digital Supply(Min), V	4.5	4.5	4.5	4.5	4.5	4.5
INL(Max), +/-LSB	1	1	1	1	1	1
Input Range(Max), V	5.5	5.5	5.5	5.5	5.5	5.5
Input Type	Single-Ended	Single-Ended	Single-Ended	Single-Ended	Single-Ended	Single-Ended
Integrated Features	N/A	N/A	N/A	N/A	N/A	N/A
Interface	SPI	SPI	SPI	SPI	SPI	SPI
Multi-Channel Configuration	Multiplexed	Multiplexed	Multiplexed	Multiplexed	Multiplexed	Multiplexed
Operating Temperature Range, C	-40 to 85,0 to 70	-40 to 85,0 to 70	-40 to 85,0 to 70	-40 to 85,0 to 70	-40 to 85,0 to 70	-40 to 85,0 to 70
Package Group	VSSOP	VSSOP	SOIC	SOIC	VSSOP	VSSOP
Package Size: mm2:W x L, PKG	8VSSOP: 15 mm2: 4.9 x 3(VSSOP)	8VSSOP: 15 mm2: 4.9 x 3(VSSOP)	8SOIC: 29 mm2: 6 x 4.9(SOIC)	8SOIC: 29 mm2: 6 x 4.9(SOIC)	8VSSOP: 15 mm2: 4.9 x 3(VSSOP)	8VSSOP: 15 mm2: 4.9 x 3(VSSOP)
Power Consumption(Typ), mW	15	15	15	15	15	15
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Reference Mode	Ext	Ext	Ext	Ext	Ext	Ext
Resolution, Bits	12	12	12	12	12	12
SINAD, dB	72	72	72	72	72	72
SNR, dB	72	72	72	72	72	72
Sample Rate (max), SPS	400kSPS	400kSPS	400kSPS	400kSPS	400kSPS	400kSPS
Sample Rate(Max), MSPS	0.4	0.4	0.4	0.4	0.4	0.4
THD(Typ), dB	-84	-84	-84	-84	-84	-84

	TLC2552CDGK	TLC2552CDGKG4	TLC2552ID	TLC2552IDG4	TLC2552IDGK	TLC2552IDGKG4
RoHS	Obediente	Obediente	Obediente	Obediente	Obediente	Obediente

Descargar
Interfacing the TLC2552 and TLV2542 to the MSP430F149
PDF, 123 Kb, Archivo publicado: feb 10, 2003
This application note discusses the features of the TLC2552 and TLV2542 ADC. An SPI interface code example for the MSP430F149 to the TLC2552 ADC, and for the MSP430F149 to the TLV2542 ADC, are also presented.
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Determining Minimum Acquisition Times for SAR ADCs, part 2
PDF, 215 Kb, Archivo publicado: marzo 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to

Serie: TLC2552 (6)

Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> Precision ADCs (<=10MSPS)