Datasheet Texas Instruments THS0842 — Ficha de datos

Fabricante	Texas Instruments
Serie	THS0842

Hojas de datos

Precios

Estado

Embalaje

Paramétricos

Parameters / Models	THS0842IPFB
# Input Channels	2
Analog Input BW, MHz	600
Architecture	Pipeline
DNL(Max), +/-LSB	2
DNL(Typ), +/-LSB	0.7
ENOB, Bits	6.8
INL(Max), +/-LSB	2.2
INL(Typ), +/-LSB	1.5
Input Buffer	No
Input Range, Vp-p	1.3
Interface	Parallel CMOS
Operating Temperature Range, C	-40 to 85
Package Group	TQFP
Package Size: mm2:W x L, PKG	48TQFP: 81 mm2: 9 x 9(TQFP)
Power Consumption(Typ), mW	320
Rating	Catalog
Reference Mode	Ext,Int
Resolution, Bits	8
SFDR, dB	52
SINAD, dB	43.3
SNR, dB	42.7
Sample Rate(Max), MSPS	40

Plan ecológico

Notas de aplicación

• Descargar
  CDCE62005 as Clock Solution for High-Speed ADCs
  PDF, 805 Kb, Archivo publicado: sept 4, 2008
  TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
• Descargar
  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, Archivo publicado: jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
• Descargar
  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, Archivo publicado: jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
• Descargar
  Noise Analysis for High Speed Op Amps (Rev. A)
  PDF, 256 Kb, Revisión: A, Archivo publicado: enero 17, 2005
  As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu

Linea modelo

Clasificación del fabricante

• Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)