Datasheet Texas Instruments SN74LVTH646 — Ficha de datos

Fabricante	Texas Instruments
Serie	SN74LVTH646

Hojas de datos

Precios

Estado

Embalaje

Paramétricos

Parameters / Models	SN74LVTH646DBLE	SN74LVTH646DW	SN74LVTH646DWG4	SN74LVTH646PWLE	SN74LVTH646PWR
Approx. Price (US$)	0.46 | 1ku			0.46 | 1ku
Bits		8	8		8
Bits(#)	8			8
F @ Nom Voltage(Max), Mhz		160	160		160
F @ Nom Voltage(Max)(Mhz)	160			160
ICC @ Nom Voltage(Max), mA		0.005	0.005		0.005
ICC @ Nom Voltage(Max)(mA)	0.005			0.005
Input Type	TTL/CMOS			TTL/CMOS
Operating Temperature Range, C		-40 to 85	-40 to 85		-40 to 85
Operating Temperature Range(C)	-40 to 85			-40 to 85
Output Drive (IOL/IOH)(Max), mA		-32/64	-32/64		-32/64
Output Drive (IOL/IOH)(Max)(mA)	-32/64			-32/64
Output Type	LVTTL			LVTTL
Package Group	SOIC TSSOP	SOIC	SOIC	TSSOP	TSSOP
Package Size: mm2:W x L, PKG		24SOIC: 160 mm2: 10.3 x 15.5(SOIC)	24SOIC: 160 mm2: 10.3 x 15.5(SOIC)		24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)
Package Size: mm2:W x L (PKG)	24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) 24SOIC: 160 mm2: 10.3 x 15.5(SOIC)			24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No	No	No
Technology Family	LVT	LVT	LVT	LVT	LVT
VCC(Max), V		3.6	3.6		3.6
VCC(Max)(V)	3.6			3.6
VCC(Min), V		2.7	2.7		2.7
VCC(Min)(V)	2.7			2.7
Voltage(Nom), V		3.3	3.3		3.3
Voltage(Nom)(V)	3.3			3.3
tpd @ Nom Voltage(Max), ns		4.7	4.7		4.7
tpd @ Nom Voltage(Max)(ns)	4.7			4.7

Plan ecológico

Notas de aplicación

• Descargar
  LVT Family Characteristics (Rev. A)
  PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
  To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
• Descargar
  LVT-to-LVTH Conversion
  PDF, 84 Kb, Archivo publicado: dic 8, 1998
  Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
• Descargar
  Bus-Hold Circuit
  PDF, 418 Kb, Archivo publicado: feb 5, 2001
  When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Linea modelo

Clasificación del fabricante

• Semiconductors> Logic> Buffer/Driver/Transceiver> Registered Transceiver