Datasheet Texas Instruments SN74LVTH573 — Ficha de datos

FabricanteTexas Instruments
SerieSN74LVTH573
Datasheet Texas Instruments SN74LVTH573

3.3-V ABT Octal Cierres transparentes tipo D con salidas de 3 estados

Hojas de datos

SN54LVTH573, SN74LVTH573 datasheet
PDF, 1.5 Mb, Revisión: H, Archivo publicado: sept 15, 2003
Extracto del documento

Precios

Estado

SN74LVTH573DBRSN74LVTH573DBRE4SN74LVTH573DWSN74LVTH573DWE4SN74LVTH573DWRSN74LVTH573DWRE4SN74LVTH573NSRSN74LVTH573PWSN74LVTH573PWG4SN74LVTH573PWRSN74LVTH573RGYR
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNoNoNoNoNoNoNoNo

Embalaje

SN74LVTH573DBRSN74LVTH573DBRE4SN74LVTH573DWSN74LVTH573DWE4SN74LVTH573DWRSN74LVTH573DWRE4SN74LVTH573NSRSN74LVTH573PWSN74LVTH573PWG4SN74LVTH573PWRSN74LVTH573RGYR
N1234567891011
Pin2020202020202020202020
Package TypeDBDBDWDWDWDWNSPWPWPWRGY
Industry STD TermSSOPSSOPSOICSOICSOICSOICSOPTSSOPTSSOPTSSOPVQFN
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PQFP-N
Package QTY200020002525200020002000707020003000
CarrierLARGE T&RLARGE T&RTUBETUBELARGE T&RLARGE T&RLARGE T&RTUBETUBELARGE T&RLARGE T&R
Device MarkingLXH573LXH573LVTH573LVTH573LVTH573LVTH573LVTH573LXH573LXH573LXH573LXH573
Width (mm)5.35.37.57.57.57.55.34.44.44.43.5
Length (mm)7.27.212.812.812.812.812.66.56.56.54.5
Thickness (mm)1.951.952.352.352.352.351.95111.9
Pitch (mm).65.651.271.271.271.271.27.65.65.65.5
Max Height (mm)222.652.652.652.6521.21.21.21
Mechanical DataDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargarDescargar

Paramétricos

Parameters / ModelsSN74LVTH573DBR
SN74LVTH573DBR
SN74LVTH573DBRE4
SN74LVTH573DBRE4
SN74LVTH573DW
SN74LVTH573DW
SN74LVTH573DWE4
SN74LVTH573DWE4
SN74LVTH573DWR
SN74LVTH573DWR
SN74LVTH573DWRE4
SN74LVTH573DWRE4
SN74LVTH573NSR
SN74LVTH573NSR
SN74LVTH573PW
SN74LVTH573PW
SN74LVTH573PWG4
SN74LVTH573PWG4
SN74LVTH573PWR
SN74LVTH573PWR
SN74LVTH573RGYR
SN74LVTH573RGYR
3-State OutputYesYesYesYesYesYesYesYesYesYesYes
Bits88888888888
F @ Nom Voltage(Max), Mhz160160160160160160160160160160160
ICC @ Nom Voltage(Max), mA55555555555
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA64/-3264/-3264/-3264/-3264/-3264/-3264/-3264/-3264/-3264/-3264/-32
Package GroupSSOPSSOPSOICSOICSOICSOICSOTSSOPTSSOPTSSOPVQFN
Package Size: mm2:W x L, PKG20SSOP: 56 mm2: 7.8 x 7.2(SSOP)20SSOP: 56 mm2: 7.8 x 7.2(SSOP)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SO: 98 mm2: 7.8 x 12.6(SO)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20VQFN: 16 mm2: 3.5 x 4.5(VQFN)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNoNoNoNoNo
Technology FamilyLVTLVTLVTLVTLVTLVTLVTLVTLVTLVTLVT
VCC(Max), V3.63.63.63.63.63.63.63.63.63.63.6
VCC(Min), V2.72.72.72.72.72.72.72.72.72.72.7
Voltage(Nom), V3.33.33.33.33.33.33.33.33.33.33.3
tpd @ Nom Voltage(Max), ns3.93.93.93.93.93.93.93.93.93.93.9

Plan ecológico

SN74LVTH573DBRSN74LVTH573DBRE4SN74LVTH573DWSN74LVTH573DWE4SN74LVTH573DWRSN74LVTH573DWRE4SN74LVTH573NSRSN74LVTH573PWSN74LVTH573PWG4SN74LVTH573PWRSN74LVTH573RGYR
RoHSObedienteObedienteObedienteObedienteObedienteObedienteObedienteObedienteObedienteObedienteObediente

Notas de aplicación

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Archivo publicado: dic 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, Archivo publicado: feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Linea modelo

Clasificación del fabricante

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Latch