Datasheet Texas Instruments SN74LVTH32374-EP — Ficha de datos

FabricanteTexas Instruments
SerieSN74LVTH32374-EP
Datasheet Texas Instruments SN74LVTH32374-EP

Producto mejorado 3.3-V Abt 32-Bit Triggered Edge-Flop tipo D con salidas de 3 estados

Hojas de datos

SN74LVTH32374-EP datasheet
PDF, 220 Kb, Archivo publicado: dic 10, 2003
Extracto del documento

Precios

Estado

CLVTH32374IGKEREPV62/04722-01XA
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNo

Embalaje

CLVTH32374IGKEREPV62/04722-01XA
N12
Pin9696
Package TypeGKEGKE
Industry STD TermBGA MICROSTARBGA MICROSTAR
JEDEC CodeR-PBGA-NR-PBGA-N
Package QTY10001000
CarrierLARGE T&RLARGE T&R
Device MarkingL374EPL374EP
Width (mm)5.55.5
Length (mm)13.513.5
Thickness (mm).9.9
Pitch (mm).8.8
Max Height (mm)1.41.4
Mechanical DataDescargarDescargar

Paramétricos

Parameters / ModelsCLVTH32374IGKEREP
CLVTH32374IGKEREP
V62/04722-01XA
V62/04722-01XA
3-State OutputYesYes
Bits3232
F @ Nom Voltage(Max), Mhz160160
ICC @ Nom Voltage(Max), mA1010
Input TypeTTLTTL
Operating Temperature Range, C-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA64/-3264/-32
Output TypeTTLTTL
Package GroupLFBGALFBGA
Package Size: mm2:W x L, PKG96LFBGA: 74 mm2: 5.5 x 13.5(LFBGA)96LFBGA: 74 mm2: 5.5 x 13.5(LFBGA)
RatingHiRel Enhanced ProductHiRel Enhanced Product
Technology FamilyLVTLVT
VCC(Max), V3.63.6
VCC(Min), V2.72.7
tpd @ Nom Voltage(Max), ns4.54.5

Plan ecológico

CLVTH32374IGKEREPV62/04722-01XA
RoHSSee ti.comSee ti.com

Notas de aplicación

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Archivo publicado: dic 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, Revisión: B, Archivo publicado: mayo 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
    PDF, 105 Kb, Revisión: A, Archivo publicado: agosto 1, 1997
    The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Kb, Archivo publicado: mayo 1, 1996
  • Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
    PDF, 209 Kb, Archivo publicado: mayo 10, 2002
    Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revisión: A, Archivo publicado: feb 6, 2015

Linea modelo

Serie: SN74LVTH32374-EP (2)

Clasificación del fabricante

  • Semiconductors> Space & High Reliability> Logic Products> Flip-Flop/Latch/Registers