Datasheet Texas Instruments SN74LVTH32373 — Ficha de datos

FabricanteTexas Instruments
SerieSN74LVTH32373
Datasheet Texas Instruments SN74LVTH32373

3.3-V ABT 32-Bit Transparente L-Type Latch con salidas de 3 estados

Hojas de datos

SN74LVTH32373 datasheet
PDF, 781 Kb, Revisión: B, Archivo publicado: dic 1, 2006
Extracto del documento

Precios

Estado

SN74LVTH32373GKERSN74LVTH32373ZKER
Estado del ciclo de vidaNRND (No recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

SN74LVTH32373GKERSN74LVTH32373ZKER
N12
Pin9696
Package TypeGKEZKE
Industry STD TermBGA MICROSTARBGA MICROSTAR
JEDEC CodeR-PBGA-NR-PBGA-N
Package QTY10001000
CarrierLARGE T&RLARGE T&R
Device MarkingHV373HV373
Width (mm)5.55.5
Length (mm)13.513.5
Thickness (mm).9.85
Pitch (mm).8.8
Max Height (mm)1.41.4
Mechanical DataDescargarDescargar

Paramétricos

Parameters / ModelsSN74LVTH32373GKER
SN74LVTH32373GKER
SN74LVTH32373ZKER
SN74LVTH32373ZKER
3-State OutputYesYes
Bits3232
F @ Nom Voltage(Max), Mhz160160
ICC @ Nom Voltage(Max), mA1010
Operating Temperature Range, C-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA64/-3264/-32
Package GroupLFBGALFBGA
Package Size: mm2:W x L, PKG96LFBGA: 74 mm2: 5.5 x 13.5(LFBGA)96LFBGA: 74 mm2: 5.5 x 13.5(LFBGA)
RatingCatalogCatalog
Schmitt TriggerNoNo
Technology FamilyLVTLVT
VCC(Max), V3.63.6
VCC(Min), V2.72.7
Voltage(Nom), V3.33.3
tpd @ Nom Voltage(Max), ns3.83.8

Plan ecológico

SN74LVTH32373GKERSN74LVTH32373ZKER
RoHSSee ti.comObediente

Notas de aplicación

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Archivo publicado: dic 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, Archivo publicado: feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Linea modelo

Serie: SN74LVTH32373 (2)

Clasificación del fabricante

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Latch