Datasheet Texas Instruments SN74LVTH32373GKER — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | SN74LVTH32373 |
| Numero de parte | SN74LVTH32373GKER |
3.3-V ABT 32-Bit Transparente L-Type Latch con salidas de 3 estados 96-LFBGA -40 a 85
Hojas de datos
SN74LVTH32373 datasheet
PDF, 781 Kb, Revisión: B, Archivo publicado: dic 1, 2006
Extracto del documento
Precios
Estado
| Estado del ciclo de vida | NRND (No recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 96 |
| Package Type | GKE |
| Industry STD Term | BGA MICROSTAR |
| JEDEC Code | R-PBGA-N |
| Package QTY | 1000 |
| Carrier | LARGE T&R |
| Device Marking | HV373 |
| Width (mm) | 5.5 |
| Length (mm) | 13.5 |
| Thickness (mm) | .9 |
| Pitch (mm) | .8 |
| Max Height (mm) | 1.4 |
| Mechanical Data | Descargar |
Paramétricos
| 3-State Output | Yes |
| Bits | 32 |
| F @ Nom Voltage(Max) | 160 Mhz |
| ICC @ Nom Voltage(Max) | 10 mA |
| Operating Temperature Range | -40 to 85 C |
| Output Drive (IOL/IOH)(Max) | 64/-32 mA |
| Package Group | LFBGA |
| Package Size: mm2:W x L | 96LFBGA: 74 mm2: 5.5 x 13.5(LFBGA) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | LVT |
| VCC(Max) | 3.6 V |
| VCC(Min) | 2.7 V |
| Voltage(Nom) | 3.3 V |
| tpd @ Nom Voltage(Max) | 3.8 ns |
Plan ecológico
| RoHS | See ti.com |
Notas de aplicación
- LVT Family Characteristics (Rev. A)PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, Archivo publicado: dic 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed. - Bus-Hold CircuitPDF, 418 Kb, Archivo publicado: feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
Linea modelo
Serie: SN74LVTH32373 (2)
- SN74LVTH32373GKER SN74LVTH32373ZKER
Clasificación del fabricante
- Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Latch