Datasheet Texas Instruments SN74LVTH18512DGGR — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | SN74LVTH18512 |
| Numero de parte | SN74LVTH18512DGGR |
Dispositivos de prueba de escaneo ABT de 3.3 V con transceptores de bus universal de 18 bits 64-TSSOP -40 a 85
Hojas de datos
3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers datasheet
PDF, 735 Kb, Revisión: B, Archivo publicado: oct 1, 1997
Extracto del documento
Precios
Estado
| Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 64 |
| Package Type | DGG |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | LVTH18512 |
| Width (mm) | 6.1 |
| Length (mm) | 17 |
| Thickness (mm) | 1.15 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Descargar |
Paramétricos
| Bits | 18 |
| F @ Nom Voltage(Max) | 160 Mhz |
| ICC @ Nom Voltage(Max) | 24 mA |
| Operating Temperature Range | -40 to 85 C |
| Output Drive (IOL/IOH)(Max) | 64/-32 mA |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 64TSSOP: 138 mm2: 8.1 x 17(TSSOP) PKG |
| Rating | Catalog |
| Technology Family | LVT |
| VCC(Max) | 3.6 V |
| VCC(Min) | 2.7 V |
| Voltage(Nom) | 3.3 V |
| tpd @ Nom Voltage(Max) | 4.9 ns |
Plan ecológico
| RoHS | Obediente |
Notas de aplicación
- Programming CPLDs Via the 'LVT8986 LASPPDF, 819 Kb, Archivo publicado: nov 1, 2005
This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to - LVT Family Characteristics (Rev. A)PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, Archivo publicado: dic 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed. - Bus-Hold CircuitPDF, 418 Kb, Archivo publicado: feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
Linea modelo
Serie: SN74LVTH18512 (2)
- 74LVTH18512DGGRE4 SN74LVTH18512DGGR
Clasificación del fabricante
- Semiconductors > Logic > Specialty Logic > Boundary Scan (JTAG) Logic