Datasheet Texas Instruments SN74LVTH182504A — Ficha de datos

Fabricante	Texas Instruments
Serie	SN74LVTH182504A

Hojas de datos

Precios

Estado

Embalaje

Paramétricos

Parameters / Models	74LVTH182504APMG4	SN74LVTH182504APM
Bits	20	20
F @ Nom Voltage(Max), Mhz	160	160
ICC @ Nom Voltage(Max), mA	27	27
Operating Temperature Range, C	-40 to 85	-40 to 85
Output Drive (IOL/IOH)(Max), mA	64/-32	64/-32
Package Group	LQFP	LQFP
Package Size: mm2:W x L, PKG	64LQFP: 144 mm2: 12 x 12(LQFP)	64LQFP: 144 mm2: 12 x 12(LQFP)
Rating	Catalog	Catalog
Technology Family	LVT	LVT
VCC(Max), V	3.6	3.6
VCC(Min), V	2.7	2.7
Voltage(Nom), V	3.3	3.3
tpd @ Nom Voltage(Max), ns	5.9	5.9

Plan ecológico

Notas de aplicación

• Descargar
  Programming CPLDs Via the 'LVT8986 LASP
  PDF, 819 Kb, Archivo publicado: nov 1, 2005
  This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to
• Descargar
  LVT Family Characteristics (Rev. A)
  PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
  To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
• Descargar
  LVT-to-LVTH Conversion
  PDF, 84 Kb, Archivo publicado: dic 8, 1998
  Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
• Descargar
  Bus-Hold Circuit
  PDF, 418 Kb, Archivo publicado: feb 5, 2001
  When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
• Descargar
  16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
  PDF, 895 Kb, Revisión: B, Archivo publicado: mayo 22, 2002
  TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
• Descargar
  Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
  PDF, 105 Kb, Revisión: A, Archivo publicado: agosto 1, 1997
  The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
• Descargar
  Understanding Advanced Bus-Interface Products Design Guide
  PDF, 253 Kb, Archivo publicado: mayo 1, 1996
• Descargar
  Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
  PDF, 209 Kb, Archivo publicado: mayo 10, 2002
  Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
• Descargar
  Live Insertion
  PDF, 150 Kb, Archivo publicado: oct 1, 1996
  Many applications require the ability to exchange modules in electronic systems without removing the supply voltage from the module (live insertion). For example an electronic telephone exchange must always remain operational even during module maintenance and repair. To avoid damaging components additional circuitry modifications are necessary. This document describes in detail the phenomena tha
• Descargar
  Input and Output Characteristics of Digital Integrated Circuits
  PDF, 1.7 Mb, Archivo publicado: oct 1, 1996
  This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given in data sheets by providing additional details regarding the characteristics of the components. This knowledge is particularly useful when for example a decision must be made as to which circuit shou

Linea modelo

Clasificación del fabricante

• Semiconductors> Logic> Specialty Logic> Boundary Scan (JTAG) Logic