Datasheet Texas Instruments SN74LVTH182502A — Ficha de datos

Fabricante	Texas Instruments
Serie	SN74LVTH182502A

Hojas de datos

Precios

Estado

Embalaje

Paramétricos

Parameters / Models	SN74LVTH182502APM	SN74LVTH182502APMR
Bits	18	18
F @ Nom Voltage(Max), Mhz	160	160
ICC @ Nom Voltage(Max), mA	24	24
Operating Temperature Range, C	-40 to 85	-40 to 85
Output Drive (IOL/IOH)(Max), mA	64/-32	64/-32
Package Group	LQFP	LQFP
Package Size: mm2:W x L, PKG	64LQFP: 144 mm2: 12 x 12(LQFP)	64LQFP: 144 mm2: 12 x 12(LQFP)
Rating	Catalog	Catalog
Technology Family	LVT	LVT
VCC(Max), V	3.6	3.6
VCC(Min), V	2.7	2.7
Voltage(Nom), V	3.3	3.3
tpd @ Nom Voltage(Max), ns	5.7	5.7

Plan ecológico

Notas de aplicación

• Descargar
  Programming CPLDs Via the 'LVT8986 LASP
  PDF, 819 Kb, Archivo publicado: nov 1, 2005
  This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to
• Descargar
  LVT Family Characteristics (Rev. A)
  PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
  To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
• Descargar
  LVT-to-LVTH Conversion
  PDF, 84 Kb, Archivo publicado: dic 8, 1998
  Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
• Descargar
  Bus-Hold Circuit
  PDF, 418 Kb, Archivo publicado: feb 5, 2001
  When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Linea modelo

Clasificación del fabricante

• Semiconductors> Logic> Specialty Logic> Boundary Scan (JTAG) Logic