Datasheet Texas Instruments SN74LVTH16835 — Ficha de datos

FabricanteTexas Instruments
SerieSN74LVTH16835
Datasheet Texas Instruments SN74LVTH16835

Controladores de bus universal de 3.3 V ABT de 18 bits con salidas de 3 estados

Hojas de datos

3.3-V ABT 18-Bit Universal Bus Drivers With 3-State Outputs datasheet
PDF, 1.0 Mb, Revisión: C, Archivo publicado: abr 7, 1999
Extracto del documento

Precios

Estado

SN74LVTH16835DGGR
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

SN74LVTH16835DGGR
N1
Pin56
Package TypeDGG
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingLVTH16835
Width (mm)6.1
Length (mm)14
Thickness (mm)1.15
Pitch (mm).5
Max Height (mm)1.2
Mechanical DataDescargar

Paramétricos

Parameters / ModelsSN74LVTH16835DGGR
SN74LVTH16835DGGR
F @ Nom Voltage(Max), Mhz160
ICC @ Nom Voltage(Max), mA5
Operating Temperature Range, C-40 to 85
Package GroupTSSOP
Package Size: mm2:W x L, PKG56TSSOP: 113 mm2: 8.1 x 14(TSSOP)
RatingCatalog
Schmitt TriggerNo
Technology FamilyLVT
VCC(Max), V3.6
VCC(Min), V2.7
Voltage(Nom), V2.5,3.3
tpd @ Nom Voltage(Max), ns5.1

Plan ecológico

SN74LVTH16835DGGR
RoHSObediente

Notas de aplicación

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Archivo publicado: dic 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, Archivo publicado: feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Linea modelo

Serie: SN74LVTH16835 (1)

Clasificación del fabricante

  • Semiconductors> Logic> Universal Bus Function> Universal Bus Driver (UBD)