Datasheet Texas Instruments SN74LVTH16500 — Ficha de datos

FabricanteTexas Instruments
SerieSN74LVTH16500
Datasheet Texas Instruments SN74LVTH16500

Transceptores de bus universal ABT de 18 bits y 3.3 V con salidas de 3 estados

Hojas de datos

SN54LVTH16500, SN74LVTH16500 datasheet
PDF, 1.1 Mb, Revisión: F, Archivo publicado: sept 11, 2003
Extracto del documento

Precios

Estado

SN74LVTH16500DGGRSN74LVTH16500DL
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNo

Embalaje

SN74LVTH16500DGGRSN74LVTH16500DL
N12
Pin5656
Package TypeDGGDL
Industry STD TermTSSOPSSOP
JEDEC CodeR-PDSO-GR-PDSO-G
Package QTY200020
CarrierLARGE T&RTUBE
Device MarkingLVTH16500LVTH16500
Width (mm)6.17.49
Length (mm)1418.41
Thickness (mm)1.152.59
Pitch (mm).5.635
Max Height (mm)1.22.79
Mechanical DataDescargarDescargar

Paramétricos

Parameters / ModelsSN74LVTH16500DGGR
SN74LVTH16500DGGR
SN74LVTH16500DL
SN74LVTH16500DL
Bits1818
F @ Nom Voltage(Max), Mhz160160
ICC @ Nom Voltage(Max), mA55
Operating Temperature Range, C-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA64/-3264/-32
Package GroupTSSOPSSOP
Package Size: mm2:W x L, PKG56TSSOP: 113 mm2: 8.1 x 14(TSSOP)56SSOP: 191 mm2: 10.35 x 18.42(SSOP)
RatingCatalogCatalog
Schmitt TriggerNoNo
Technology FamilyLVTLVT
VCC(Max), V3.63.6
VCC(Min), V2.72.7
Voltage(Nom), V3.33.3
tpd @ Nom Voltage(Max), ns3.73.7

Plan ecológico

SN74LVTH16500DGGRSN74LVTH16500DL
RoHSObedienteObediente

Notas de aplicación

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Archivo publicado: dic 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, Archivo publicado: feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Linea modelo

Serie: SN74LVTH16500 (2)

Clasificación del fabricante

  • Semiconductors> Logic> Universal Bus Function> Universal Bus Transceiver (UBT)