Datasheet Texas Instruments SN74LVTH16373-EP — Ficha de datos

FabricanteTexas Instruments
SerieSN74LVTH16373-EP
Datasheet Texas Instruments SN74LVTH16373-EP

Producto mejorado Cierres tipo D transparentes Abt de 3,3 V y 16 bits con salidas de 3 estados

Hojas de datos

SN74LVTH16373-EP 3.3-V ABT 16-Bit Transparent D-Type Latch With Tri-State Outputs datasheet
PDF, 945 Kb, Revisión: B, Archivo publicado: jun 29, 2016
Extracto del documento

Precios

Estado

CLVTH16373IDGGREPCLVTH16373IDLREPCLVTH16373MGQLREPV62/04712-01XEV62/04712-01YEV62/04712-02ZA
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNoNoNo

Embalaje

CLVTH16373IDGGREPCLVTH16373IDLREPCLVTH16373MGQLREPV62/04712-01XEV62/04712-01YEV62/04712-02ZA
N123456
Pin484856484856
Package TypeDGGDLGQLDGGDLGQL
Industry STD TermTSSOPSSOPBGA MICROSTAR JUNIORTSSOPSSOPBGA MICROSTAR JUNIOR
JEDEC CodeR-PDSO-GR-PDSO-GR-PBGA-NR-PDSO-GR-PDSO-GR-PBGA-N
Package QTY200010002000200010002000
CarrierLARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&R
Device MarkingLH16373EPLH16373EPH16373MEPLH16373EPLH16373EPH16373MEP
Width (mm)6.17.494.56.17.494.5
Length (mm)12.515.88712.515.887
Thickness (mm)1.152.59.751.152.59.75
Pitch (mm).5.635.65.5.635.65
Max Height (mm)1.22.7911.22.791
Mechanical DataDescargarDescargarDescargarDescargarDescargarDescargar

Paramétricos

Parameters / ModelsCLVTH16373IDGGREP
CLVTH16373IDGGREP
CLVTH16373IDLREP
CLVTH16373IDLREP
CLVTH16373MGQLREP
CLVTH16373MGQLREP
V62/04712-01XE
V62/04712-01XE
V62/04712-01YE
V62/04712-01YE
V62/04712-02ZA
V62/04712-02ZA
3-State OutputYesYesYesYesYesYes
Bits161616161616
F @ Nom Voltage(Max), Mhz160160160160160160
ICC @ Nom Voltage(Max), mA555555
Input TypeTTLTTLTTLTTLTTLTTL
Operating Temperature Range, C-40 to 85,-55 to 125-40 to 85,-55 to 125-40 to 85,-55 to 125-40 to 85,-55 to 125-40 to 85,-55 to 125-40 to 85,-55 to 125
Output Drive (IOL/IOH)(Max), mA64/-3264/-3264/-3264/-3264/-3264/-32
Output TypeTTLTTLTTLTTLTTLTTL
Package GroupTSSOPSSOPBGA MICROSTAR JUNIORTSSOPSSOPBGA MICROSTAR JUNIOR
Package Size: mm2:W x L, PKG48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)56BGA MICROSTAR JUNIOR: 32 mm2: 4.5 x 7(BGA MICROSTAR JUNIOR)48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)56BGA MICROSTAR JUNIOR: 32 mm2: 4.5 x 7(BGA MICROSTAR JUNIOR)
RatingHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced Product
Technology FamilyLVTLVTLVTLVTLVTLVT
VCC(Max), V3.63.63.63.63.63.6
VCC(Min), V2.72.72.72.72.72.7
tpd @ Nom Voltage(Max), ns3.83.83.83.83.83.8

Plan ecológico

CLVTH16373IDGGREPCLVTH16373IDLREPCLVTH16373MGQLREPV62/04712-01XEV62/04712-01YEV62/04712-02ZA
RoHSObedienteObedienteSee ti.comObedienteObedienteSee ti.com

Notas de aplicación

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Archivo publicado: dic 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, Revisión: B, Archivo publicado: mayo 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
    PDF, 105 Kb, Revisión: A, Archivo publicado: agosto 1, 1997
    The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Kb, Archivo publicado: mayo 1, 1996
  • Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
    PDF, 209 Kb, Archivo publicado: mayo 10, 2002
    Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, Revisión: A, Archivo publicado: feb 6, 2015

Linea modelo

Clasificación del fabricante

  • Semiconductors> Space & High Reliability> Logic Products> Flip-Flop/Latch/Registers