Datasheet Texas Instruments CLVTH16373IDGGREP — Ficha de datos
| Fabricante | Texas Instruments |
| Serie | SN74LVTH16373-EP |
| Numero de parte | CLVTH16373IDGGREP |
Producto mejorado Cierres tipo D transparentes Abt de 3,3 V de 16 bits con salidas de 3 estados 48-TSSOP -40 a 85
Hojas de datos
SN74LVTH16373-EP 3.3-V ABT 16-Bit Transparent D-Type Latch With Tri-State Outputs datasheet
PDF, 945 Kb, Revisión: B, Archivo publicado: jun 29, 2016
Extracto del documento
Precios
Estado
| Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) |
| Disponibilidad de muestra del fabricante | No |
Embalaje
| Pin | 48 |
| Package Type | DGG |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | LH16373EP |
| Width (mm) | 6.1 |
| Length (mm) | 12.5 |
| Thickness (mm) | 1.15 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Descargar |
Paramétricos
| 3-State Output | Yes |
| Bits | 16 |
| F @ Nom Voltage(Max) | 160 Mhz |
| ICC @ Nom Voltage(Max) | 5 mA |
| Input Type | TTL |
| Operating Temperature Range | -40 to 85,-55 to 125 C |
| Output Drive (IOL/IOH)(Max) | 64/-32 mA |
| Output Type | TTL |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) PKG |
| Rating | HiRel Enhanced Product |
| Technology Family | LVT |
| VCC(Max) | 3.6 V |
| VCC(Min) | 2.7 V |
| tpd @ Nom Voltage(Max) | 3.8 ns |
Plan ecológico
| RoHS | Obediente |
Notas de aplicación
- LVT Family Characteristics (Rev. A)PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, Archivo publicado: dic 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed. - 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)PDF, 895 Kb, Revisión: B, Archivo publicado: mayo 22, 2002
TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa - Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)PDF, 105 Kb, Revisión: A, Archivo publicado: agosto 1, 1997
The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi - Understanding Advanced Bus-Interface Products Design GuidePDF, 253 Kb, Archivo publicado: mayo 1, 1996
- Power-Up 3-State (PU3S) Circuits in TI Standard Logic DevicesPDF, 209 Kb, Archivo publicado: mayo 10, 2002
Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features - Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revisión: A, Archivo publicado: feb 6, 2015
Linea modelo
Serie: SN74LVTH16373-EP (6)
- CLVTH16373IDGGREP CLVTH16373IDLREP CLVTH16373MGQLREP V62/04712-01XE V62/04712-01YE V62/04712-02ZA
Clasificación del fabricante
- Semiconductors > Space & High Reliability > Logic Products > Flip-Flop/Latch/Registers