Datasheet Texas Instruments SN74LVTH162541 — Ficha de datos

Fabricante	Texas Instruments
Serie	SN74LVTH162541

Búferes / controladores ABT de 16 bits y 3.3 V con salidas de 3 estados

Hojas de datos

PDF, 313 Kb, Revisión: F, Archivo publicado: nov 1, 2006

Extracto del documento

	SN74LVTH162541DGGR	SN74LVTH162541DL	SN74LVTH162541DLR
Estado del ciclo de vida	Activo (Recomendado para nuevos diseños)	Activo (Recomendado para nuevos diseños)	Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricante	No	No	No

Parameters / Models	SN74LVTH162541DGGR	SN74LVTH162541DL	SN74LVTH162541DLR
Bits	16	16	16
F @ Nom Voltage(Max), Mhz	160	160	160
ICC @ Nom Voltage(Max), mA	0.005	0.005	0.005
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85
Output Drive (IOL/IOH)(Max), mA	-12/12	-12/12	-12/12
Package Group	TSSOP	SSOP	SSOP
Package Size: mm2:W x L, PKG	48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)	48SSOP: 164 mm2: 10.35 x 15.88(SSOP)	48SSOP: 164 mm2: 10.35 x 15.88(SSOP)
Rating	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No
Technology Family	LVT	LVT	LVT
VCC(Max), V	3.6	3.6	3.6
VCC(Min), V	2.7	2.7	2.7
Voltage(Nom), V	3.3	3.3	3.3
tpd @ Nom Voltage(Max), ns	4.1	4.1	4.1

	SN74LVTH162541DGGR	SN74LVTH162541DL	SN74LVTH162541DLR
RoHS	Obediente	Obediente	Obediente

Descargar
LVT Family Characteristics (Rev. A)
PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
Descargar
LVT-to-LVTH Conversion
PDF, 84 Kb, Archivo publicado: dic 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
Descargar
Bus-Hold Circuit
PDF, 418 Kb, Archivo publicado: feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Serie: SN74LVTH162541 (3)