Datasheet Texas Instruments SN74LVT8996-EP — Ficha de datos

FabricanteTexas Instruments
SerieSN74LVT8996-EP
Datasheet Texas Instruments SN74LVT8996-EP

Producto mejorado 3.3-V Abt 10-Bit Multidrop-Addressable Ieee Std 1149.1 Tap Transceptor

Hojas de datos

SN74LVT8996-EP datasheet
PDF, 758 Kb, Archivo publicado: sept 3, 2003
Extracto del documento

Precios

Estado

SN74LVT8996IPWREPV62/04644-01YE
Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)Activo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNoNo

Embalaje

SN74LVT8996IPWREPV62/04644-01YE
N12
Pin2424
Package TypePWPW
Industry STD TermTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-G
Package QTY20002000
CarrierLARGE T&RLARGE T&R
Device MarkingLT8996EPLT8996EP
Width (mm)4.44.4
Length (mm)7.87.8
Thickness (mm)11
Pitch (mm).65.65
Max Height (mm)1.21.2
Mechanical DataDescargarDescargar

Paramétricos

Parameters / ModelsSN74LVT8996IPWREP
SN74LVT8996IPWREP
V62/04644-01YE
V62/04644-01YE
Bits1010
ICC @ Nom Voltage(Max), mA2020
Input TypeTTL/CMOSTTL/CMOS
Operating Temperature Range, C-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA64/-3264/-32
Output TypeLVTTLLVTTL
Package GroupTSSOPTSSOP
Package Size: mm2:W x L, PKG24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)
RatingHiRel Enhanced ProductHiRel Enhanced Product
Technology FamilyLVTLVT
VCC(Max), V3.63.6
VCC(Min), V2.72.7

Plan ecológico

SN74LVT8996IPWREPV62/04644-01YE
RoHSObedienteObediente

Notas de aplicación

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Archivo publicado: dic 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

Linea modelo

Serie: SN74LVT8996-EP (2)

Clasificación del fabricante

  • Semiconductors> Space & High Reliability> Logic Products> Specialty Logic Products> Boundary Scan (JTAG)