Datasheet Texas Instruments SN74LVT8996DWR — Ficha de datos

FabricanteTexas Instruments
SerieSN74LVT8996
Numero de parteSN74LVT8996DWR
Datasheet Texas Instruments SN74LVT8996DWR

Puertos de exploración direccionables ABT de 3,3 bits y 10 V Transceptor TAP IEEE STD 1149.1 (JTAG) multidrop direccionable 24-SOIC -40 a 85

Hojas de datos

3.3-V 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE Std 1149.1 (JTAG) datasheet
PDF, 1.3 Mb, Revisión: A, Archivo publicado: dic 2, 1999
Extracto del documento

Precios

Estado

Estado del ciclo de vidaActivo (Recomendado para nuevos diseños)
Disponibilidad de muestra del fabricanteNo

Embalaje

Pin24
Package TypeDW
Industry STD TermSOIC
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingLVT8996
Width (mm)7.5
Length (mm)15.4
Thickness (mm)2.35
Pitch (mm)1.27
Max Height (mm)2.65
Mechanical DataDescargar

Paramétricos

Bits10
ICC @ Nom Voltage(Max)20 mA
Operating Temperature Range-40 to 85 C
Output Drive (IOL/IOH)(Max)64/-32 mA
Package GroupSOIC
Package Size: mm2:W x L24SOIC: 160 mm2: 10.3 x 15.5(SOIC) PKG
RatingCatalog
Technology FamilyLVT
VCC(Max)3.6 V
VCC(Min)2.7 V

Plan ecológico

RoHSObediente

Notas de aplicación

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, Archivo publicado: dic 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

Linea modelo

Clasificación del fabricante

  • Semiconductors > Logic > Specialty Logic > Boundary Scan (JTAG) Logic