Datasheet Texas Instruments SN74LVT8980A-EP — Ficha de datos
Fabricante | Texas Instruments |
Serie | SN74LVT8980A-EP |
Producto mejorado Controladores de bus de prueba integrados Ieee Std 1149.1 (Jtag) Tap Masters
Hojas de datos
SN74LVT8980A-EP datasheet
PDF, 830 Kb, Revisión: A, Archivo publicado: oct 29, 2003
Extracto del documento
Precios
Estado
SN74LVT8980AIDWREP | V62/03668-01XE | |
---|---|---|
Estado del ciclo de vida | Activo (Recomendado para nuevos diseños) | Activo (Recomendado para nuevos diseños) |
Disponibilidad de muestra del fabricante | No | No |
Embalaje
SN74LVT8980AIDWREP | V62/03668-01XE | |
---|---|---|
N | 1 | 2 |
Pin | 24 | 24 |
Package Type | DW | DW |
Industry STD Term | SOIC | SOIC |
JEDEC Code | R-PDSO-G | R-PDSO-G |
Package QTY | 2000 | 2000 |
Carrier | LARGE T&R | LARGE T&R |
Device Marking | LVT8980AEP | LVT8980AEP |
Width (mm) | 7.5 | 7.5 |
Length (mm) | 15.4 | 15.4 |
Thickness (mm) | 2.35 | 2.35 |
Pitch (mm) | 1.27 | 1.27 |
Max Height (mm) | 2.65 | 2.65 |
Mechanical Data | Descargar | Descargar |
Paramétricos
Parameters / Models | SN74LVT8980AIDWREP | V62/03668-01XE |
---|---|---|
Bits | 8 | 8 |
ICC @ Nom Voltage(Max), mA | 7 | 7 |
Input Type | TTL/CMOS | TTL/CMOS |
Operating Temperature Range, C | -40 to 85 | -40 to 85 |
Output Drive (IOL/IOH)(Max), mA | 64/-32 | 64/-32 |
Output Type | LVTTL | LVTTL |
Package Group | SOIC | SOIC |
Package Size: mm2:W x L, PKG | 24SOIC: 160 mm2: 10.3 x 15.5(SOIC) | 24SOIC: 160 mm2: 10.3 x 15.5(SOIC) |
Rating | HiRel Enhanced Product | HiRel Enhanced Product |
Technology Family | LVT | LVT |
VCC(Max), V | 3.6 | 3.6 |
VCC(Min), V | 2.7 | 2.7 |
tpd @ Nom Voltage(Max), ns | 30 | 30 |
Plan ecológico
SN74LVT8980AIDWREP | V62/03668-01XE | |
---|---|---|
RoHS | Obediente | Obediente |
Notas de aplicación
- LVT Family Characteristics (Rev. A)PDF, 98 Kb, Revisión: A, Archivo publicado: marzo 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, Archivo publicado: dic 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
Linea modelo
Serie: SN74LVT8980A-EP (2)
Clasificación del fabricante
- Semiconductors> Space & High Reliability> Logic Products> Specialty Logic Products> Boundary Scan (JTAG)